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An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 $\mu$m CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8–3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13–18.9 and 24–40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

In this paper, a multiband low-noise amplifier (LNA) with capability of band tuning is proposed to support the Mobile WiMAX (IEEE 802.16e) standard associated with a large IIP3 at RF frequencies using multi-gated linearization techniques. Proposed LNA architecture has been optimized in terms of linearity based on a comparative analysis between four tunable LNA structures. In addition, a general survey is performed on linearization techniques (multiple-gated transistors, Derivative Superposition (DS), Modified DS). Proposed LNA is constituted of multi-gated linearization technique. Design and simulations have been realized in 0.13 μm RF CMOS process considering a power supply of 1.2 V. Proposed LNA exhibits an IIP3 of +8.8 dBm, +14.3 dBm, and +6.4 dBm at the lower, middle, and upper bands of WIMAX, respectively. It results in a power gain of 10 dB, a noise figure below 2.5 dB and S₁₁ of -11.5 dB, -8.6 dB, and -12.7 dB at the lower, middle, and upper bands. The related power dissipations are 10 mW, 9.9 mW, and 9.4 mW at the lower, middle, and upper bands, respectively.

This paper presents a highly-integrated transceiver with a differential structure for C-band (5–6GHz) radar application using a switchless and baluns-embedded configuration. To reduce the noise figure (NF) in receiver (Rx) mode and enhance the output power in transmitter (Tx) mode, the balun at RF port is embedded into the low-noise amplifier (LNA) and the power amplifier (PA), respectively. Besides, the RF switch is removed by designing the matching networks that both LNA and PA can share. The same topology is also adopted at the IF port. To achieve a high image rejection ratio (IRR), a Hartley architecture using polyphase filters (PPFs) is adopted. The proposed transceiver has been implemented in 1P6M 0.18-$\mu$m CMOS process. The receiver achieves 6.9-dB NF, $-$7.5-dBm IIP₃ and 26.3-dB gain with three-step digital gain controllability. Also the measured IRR is better than 41dBc. The transmitter achieves 9.6-dBm output power and 19.2-dB gain. The chip consumes 106mA in the Rx mode and 141mA in the Tx mode from the 3.3-V power supply.

In this paper, an evolutionary computation-based optimal design of low power, high gain inductive source degenerated CMOS cascode low noise amplifier (LNA) circuit is presented for 2.4GHz frequency. The main challenge for the design of radio frequency (RF) LNAs at nanometer range is the thermal noise generated in the short-channel MOSFETs. The short-channel effects (SCEs), such as velocity saturation and channel-length modulation, are considered for the design of CMOS LNA. The evolutionary algorithm taken for this work is Moth-Flame Optimization (MFO) algorithm. MFO is utilized for the optimization of noise figure (NF) while satisfying all the other design performance parameters like gain, matching parameters at input/output, power dissipation, linearity, stability. Optimal values of the sizes of the transistors and other design parameters in designing the LNA circuit are also obtained from the MFO algorithm. The CMOS LNA circuit is designed by using MFO-based optimal design parameters in CADENCE software with a standard 0.18$\mu$m CMOS process. The designed LNA shows a gain of 15.28dB, NF of 0.376dB, the power dissipation of 936$\mu$W and IIP3 of $-4.36$dBm at 2.4GHz. The designed LNA achieves better trade-off which results in an FOM of 42.3mW${}^{-1}$ and may be useful in the receiver module of IEEE 802.15.4 for WLAN applications.

In traditional phased-array T/R modules, front-end modules such as limiter, low-noise amplifier (LNA) and RF switch are generally implemented by independent devices, with low integration and high cost. This paper realizes the integration of all receiver functional modules in the 0.13$\mu$m CMOS SOI process, including RF switch, LNA with limiter, 6-bit digital controlled attenuator and phase shifter, and drive amplifier. The LNA integrates a limiting function, which can suffer 2W continuous wave. Fast charge–discharge circuit is applied to the low insertion loss RF switch, which greatly reduces the switching time. The phase shifter adopts a double balanced switch used for 180^∘ phase shift, which significantly reduces the phase error. The measured channel gain is about 28dB with an NF about 2.3dB and an IP1 dB above $-$14dBm. The state error of attenuator is less than $+∕-0.6$dB with step error less than $+∕-0.3$dB. The RMS phase error of phase shifter is less than 1.8 degrees. The fully integrated transceiver IC occupies an area of $5\times 5.6$mm². This receiver draws only 128mA with a 3.3V power supply.