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State encoding problem assigns binary codes to given symbolic states such that a specific objective function such as power dissipation can be optimized in the final implementation. In this paper, we present a novel encoding technique to minimize the switching activity of any given FSMs for low power design. The experiments with standard benchmarks show that the proposed algorithm is a significant improvement over previous ones.

In this paper, we present an address bus coding method to reduce dynamic power dissipations and delay faults at on-chip applications. The purpose of the proposed new coding technique is to diminish the switching and coupling activities on instruction address busses effectively. The proposed bus coding method is called the exclusive-OR and bus inverter transition signaling (XOR–BITS) code. The XOR–BITS code has four advantages. Firstly, it can save a large number of switching activities. Secondly, it can also save a large number of coupling activities. Thirdly, its architecture belongs to a low-complexity architecture. Finally, its delay is short after optimizations. Experimental results show that the XOR–BITS coding indicates an average reduction in 78.5% switching activities and 21.9% coupling activities on instruction address busses. It surpasses the other address coding methods in total power dissipations when the load capacitance is more than 1 pF/bit with the TSMC 0.13 μm CMOS technology. For a 50 pF/bit load capacitance, it achieves a 74.9% average reduction in total power dissipations, compared with the un-coded schemes by using seven benchmarks. Similarly, our method also surpasses the other address bus coding methods with the TSMC 0.18 μm CMOS technology.

Multipliers are the building blocks of every digital signal processor (DSP). The performance of any digital system is dependent on the adder design and to a large extent on the multiplier block. Area and power dissipation are the major considerations in a multiplier design due to its complexity. In this paper, an efficient multiplier “bypass zero feed multiplicand directly,” based on shift-add multiplication, has been proposed for low-power application. As the shift-add multiplication is a repetitive process of addition, the implementation time of an adder is reduced by using the proposed parallel prefix adders designed based on revised Ling equations. The proposed 8-bit, 16-bit and 32-bit multipliers are implemented using 180-nm and 90-nm CMOS technologies. Simulation results reveal that the proposed multiplier is fast and lowers the power by 35% predominantly for a 32-bit multiplier.

Testing modern integrated circuit (IC) is challenging with introduction of System-on Chip (SOC). Enormous test pattern count is required to authenticate the IC which inflates power consumption. Henceforth, it is mandatory to incorporate power minimization techniques at circuit design phase. Optimizing test patterns is one such effective technique that curtails test power without altering circuit design. In this paper, a new test pattern reordering algorithm is proposed based on Recurrent Neural Network. Hopfield Neural Network (HNN) constitutes an optimized solution for solving traveling salesman problem (TSP). Since, test pattern reordering can be interpreted as TSP, optimized test pattern order is attained with HNN. Energy function of this algorithm falls into local minimum, so to eradicate this issue, the algorithm is modified. Test patterns are reordered with minimal hamming distance among consecutive test patterns. The proposed algorithm is implemented in ISCAS’89 Sequential Benchmark circuits. Experimental results prove that significant reduction in transition count is accomplished with proposed algorithm without compromising fault coverage.