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Controlling the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reliability, performance and power of chip, and increases the packaging cost. In this work, we address a new problem of thermal-aware functional module binding in high-level synthesis, in which the objective is to minimize the peak temperature of the chip. Two key contributions are (1) to solve the binding problem with the primary objective of minimizing the "peak" switched capacitance of modules and the secondary objective of minimizing the "total" switched capacitance of modules and (2) to control the switched capacitances with respect to the floorplan of modules in a way to minimize the "peak" heat diffusion between modules. For (1), our proposed thermal-aware binding algorithm, called TA-b, formulates the thermal-aware binding problem into a problem of repeated utilization of network flow method, and solve it effectively. For (2), TA-b is extended, called TA-bf, to take into account a given floorplan information of functional modules, if exists, of modules to be practically effective. Through experiments using a set of benchmarks, it is shown that TA-bf is able to use 10.1°C and 11.8°C lower peak temperature on the average, compared to that of the conventional low-power and thermal-aware methods, which target to minimizing total switched capacitance only in Ref. 20 and to minimizing peak switched capacitance only in Ref. 16, respectively. Additionally, we confirm, from the experiments, that the reduced peak temperature saves leakage power significantly, implying that controlling chip temperature is critically important for reducing leakage current as well.

Present study deals with the development of an artificial neural network (ANN)-based technique for tea quality quantification by monitoring fermentation and drying condition of the tea processing stages. An RS485 network-based instrumentation system has been developed and implemented for data collection for these two stages. Three calibrated sensor nodes are installed in the fermentation room due to its larger floor area to collect temperature and relative humidity (RH). Dryer inlet temperature is recorded using a calibrated thermocouple-based sensor node. From seven input parameters and target quality data obtained from tea taster, the ANN model has been developed to find the correlation between the process condition and the tea quality. From the correlation study, more than 90% classification rate is obtained from the model. The model is also validated with some independent data showing more than 60% correlation. Error in terms of root mean square error (RMSE) is about 0.17. This model will be helpful for improvement of tea quality.

The work in this paper presents the analyses of temperature-dependent simultaneous switching noise (SSN) and IR-Drop in multilayer graphene nanoribbon (MLGNR) power interconnects for 16nm ITRS technology node. A $10\times 10$ standard cell-based integrated circuit is designed to analyze the SSN and IR-Drop using the proposed temperature-dependent model of MLGNR and Cu interconnect for 10$\mu$m interconnect length at temperatures (233K, 300K and 378K). Our analysis shows that MLGNR exhibits ($\sim 1.5$–$2\times$) less SSN and ($\sim 1.5$–$3\times$) less IR-Drop as compared with traditional Cu-based power interconnects. Our analysis also shows that the average percentage of reduction in peak SSN is 52–32% (at 233K), 53–32% (at 300K) and 52–30% (at 378K) less in MLGNR compared with traditional Cu-based power interconnect and the average percentage of reduction in peak IR-Drop in MLGNR is 54–31% (at 233K), 57–29% (at 300K) and 57–26% (at 378K) less than that of Cu-based power interconnects.

In this paper, a fine-grained scheduling approach to enhance lifetime reliability of multiprocessor systems is presented. Lifetime reliability is an important and emerging concern arising with advances in technology due to the increase in power density. As a result, temperature variation accelerates wear-out, leading to system failures. The antagonistic relation of lifetime reliability with other design parameters of multiprocessor systems, such as power consumption and temperature, makes its improvement more challenging. Lifetime reliability enhancement approaches are considered at different levels of abstractions and for various system components. Our proposed scheduling method extracts the precise low-level information of lifetime reliability from determined blocks of processing cores and utilizes them at system-level to study the system state criticality at a low-performance cost. Based on the online periodic monitoring, our proposed scheduling approach applies control actions to improve lifetime reliability of the system according to its effective parameters. To demonstrate the effectiveness of our proposed scheduling approach in improving lifetime reliability and compare it to the previous related research, several experiments are considered. To simulate the target multiprocessor system and the proposed approach, the Enhanced Super ESCalar (ESESC) simulator for computer architecture tool is utilized. The experimental results show that employing our proposed scheduling method improves lifetime reliability at about 54$\%$. Moreover, it causes 14% and 12% enhancement in temperature and power consumption. Furthermore, we perform a Monte Carlo-based simulation to validate the proposed scheduling approach and generalize it to other applications at very low-performance overhead. Experimental results show that Monte Carlo simulation extremely decreases the execution time rather than ESESC which makes utilizing our scheduling approach reasonable in large applications.

This paper analyzes the signal delay and relative stability of multilayer graphene nanoribbon (MLGNR) interconnects dependent on temperature at global lengths. A thermally aware driver interconnect load (DIL) system, constituted by equivalent single conductor (ESC) model along with mathematical equations, is proposed to convert multi-conductor transmission circuit into single transmission line of MLGNR. The temperature-dependent analytical delay model of MLGNR is evaluated and the obtained outcomes are compared with the simulated results. The analytical and simulated results are obtained at global interconnect length (2000-$\mu$m) for 32nm, 22nm and 16nm nodes of technology under 200–500K temperature range of MLGNR. The simulation and analytical results reveal that the outcomes of the two models correspond well. The trend of the models shows the increase in delay with the rising temperature levels (200–500K) for three different nodes of technology. Further, relative stability analysis of MLGNR as interconnect line at three different technological nodes from 500–2000-$\mu$m lengths is examined.

This paper investigates In${}_{0.7}$Ga${}_{0.3}$As/Ga${}_{0.5}$As${}_{0.5}$Sb-based Heterojunction Tunnel Field Effect Transistor with ferroelectric dielectric as stack layer, namely Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) for the first time for performance and reliability. Ferroelectric gate dielectric has been inculcated in the device design in addition to the doping of Ga${}_{0.5}$As${}_{0.5}$Sb in the source region and In${}_{0.7}$Ga${}_{0.3}$As in the drain region, respectively. The performance of the proposed device is quantified in terms of DC electrical parameters and short channel parameters. The reliability analysis of the proposed device has been carried out in terms of influence of variations of interface trap charges, gate-source overlap length and temperature on the device transfer characteristics. From the simulation results, it can be manifested that the proposed device presents superior DC electrical characteristic and reduced short channel effects as compared to the GaSb/Si Dual Material Stacked Double Gate Heterojunction TFET (GaSb/Si DMSDG-HJTFET), under the influence of group III–V materials and ferroelectric gate dielectric. In addition to this, the proposed device depicts elevated immunity to presence of interface trap charges at the interface, variations in gate-source overlap length and temperature variations as well. The implication of TiO₂ as dielectric stack over SiO₂ provides exceptional capacitive coupling at the interface and thus assists in the improvement of electrical characteristics of the device by enhancing the electric field. The outcome of the simulation results presents that Ga${}_{0.5}$As${}_{0.5}$Sb/In${}_{0.7}$Ga${}_{0.3}$As-based Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) can prove to be a competitive alternative for high performance applications with improved reliability. The design and simulation of the proposed device structure has been executed using technology computer-aided design (TCAD) tool.