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With the development of smart grids, the demand for wire condition monitoring is increasing. However, traditional monitoring methods face problems such as insufficient real-time performance, limited data analysis capabilities, and lack of intelligence. The data source of this paper is various sensors installed on-site on the main transmission lines in City A. The collection objects are mainly temperature, humidity, and wind speed, and the collection period is from January 2024 to June 2024. In the subsequent data processing and analysis process, the raw data undergoes preprocessing, including data cleaning, normalization, trend removal, and outlier handling, to ensure the accuracy and reliability of the data. This paper uses deep belief networks to capture feature information from wire state data through multi-layer nonlinear mapping and classify it. Additionally, a recurrent neural network is employed to dynamically predict wire state by dividing the input sequence into fixed-length subsequences. The results show that the average response time of the monitoring system based on deep belief networks is 182.7ms, which is 67ms shorter than traditional monitoring systems and significantly reduces the missed detection rate of potential faults. The intelligent wire condition monitoring system studied in this paper has improved the safety and reliability of power infrastructure.

Parafrase-2 is a vectorizing/parallelizing compiler implemented as a source to source code restructurer. This paper discusses the organization of Parafrase-2 and goals of the project. Specific topics discussed are : dependence analysis, timing and overhead analysis, interprocedural analysis, automatic scheduling and the graphical user interface.

Modeling of CMOS inverters and consequently, CMOS gates, is a critical task for improving accuracy and speed of simulation in modern sub-100 nm digital circuits. One of the key factors that determine the operation of a CMOS structure is the influence of the input-to-output coupling capacitance, also called overshooting effect. In this paper, an analytical model for this effect is presented, that computes the time period which is necessary to eliminate the extra output charge transferred through the input-to-output capacitance at the beginning of the switching process in a CMOS inverter. In addition, the maximum or minimum output voltage (depending on the considered edge) is analytically computed. The derived model is based on analytical expressions of the CMOS inverter output voltage waveform, which include the influences of both transistor currents and the input-to-output (gate-to-drain) coupling and load capacitances. An accurate version of the alpha-power law MOSFET model is used to relate the terminal voltages to the drain current in sub-100 nm devices, with an extension for varying transistor widths. The resulting model also accounts for the influences of input voltage transition time, transistors' sizes, as well as device carrier velocity saturation and narrow-width effects. The results produced by the presented model for three sub-100 nm CMOS technologies, several input voltage transition times, capacitive loads and device sizes, show very good agreement with BSIM4 HSPICE simulations.

Over time, more and more systems are becoming mixed-criticality systems. As the complexity and size of these systems grow, computation/communication resources should be more efficient than with traditional systems. Time-triggered (TT) Ethernet is a communication infrastructure that enables the use of a single physical communication infrastructure for distributed mixed-criticality applications while providing timely determinism. TTEthernet distinguishes between two traffic categories: The standard event-triggered (ET) traffic and the TT traffic. The latter, for which higher priority is granted, is subject to strong timing guarantees because of strict-periodicity constraint which fixes start-time cycles of TT messages. In addition, messages in an ET Ethernet traffic, which are of lower priority, have a minimum time interval between their transmission. The focus of this paper is on the timing analysis of a TTEthernet traffic by proposing: (i) A feasibility condition allowing to assess the timing requirements of TT messages. (ii) A schedulability condition allowing to check the schedulability of ET messages by taking into account of TT messages scheduling and idle times.

Based on system execution traces, this paper presents a dynamic approach for visualizing and debugging timing constraint violations occurring in distributed real-time systems. The system execution traces used for visualization and debugging are collected during the execution of a target program in such a way that its run-time behavior is not interfered with. This is made possible by our non-interference distributed real-time monitoring system which is capable of collecting system’s run-time traces by monitoring and fetching the data passing through the internal buses of a target system. After the run-time data has been collected, the visualization and debugging activities then proceeded. The timing behavior of a target program is visualized as two graphs—the Colored Process Interaction Graph (CPIG) and the Dedicated Colored Process Interaction Graph (DCPIG). The CPIG depicts the timing behavior of a target program by graphically representing interprocess relationships during their communication and synchronization. The DCPIG can reduce visualization and debugging complexity by focusing on the portion of a target program which has direct or indirect correspondence with an imposed timing constraint. With the help of the CPIG and the DCPIG, a timing analysis method is used for computing the system-related timing statistics and analyzing the causes of timing constraint violations. A visualization and debugging system, called VDS, has been implemented using OpenWindows on Sun-4’s/UNIX workstations.