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Nanotube structures are unprecedented in their stability and current-carrying capacity at intense driving fields. A comprehensive understanding of electron conduction from equilibrium through to the high-driving-field regime is needed. We present a microscopically conserving quantum-kinetic description of transport for ohmically contacted carbon nanotubes. The approach is computationally straightforward and can describe nonequilibrium response over a wide range of parameters. We have analyzed the interplay of degeneracy and scattering dynamics on gate-controlled conduction in the one-dimensional channel, and have determined transconductances.

This paper focuses on testing the reliability of a Strained Superjunction Vertical Single diffused MOS (s-SJVSDMOS) at high-temperature. It provides an in-depth study of the device behavior at high-temperatures specifically at 300, 350 and 400 K. The s-SJVSDMOS is simulated in 2D T-CAD simulator and the outcomes are extracted. The variation of the extracted parameters with temperature is explored. The electrical and channel characteristics of the device are analyzed here. From the discussion, it was deduced that at high-temperature the device exhibits analogous characteristics as at room-temperature condition.

In this paper, for the first time, changes in the effective mass (EM) of electron and hole with mole fraction are taken into account for extracting the benchmarking parameters of analog/radio frequency (RF) and high-frequency noise performance of junctionless (JL)-Ga${}_x$In${}_{1-x}$As/GaAs via simulation. In the JL-Ga${}_x$In${}_{1-x}$As/GaAs structure, considering changes in the effective mass with mole fraction is called a with-EM state, while the JL-Ga${}_x$In${}_{1-x}$As/GaAs structure without considering the changes in effective mass with mole fraction is called a without-EM state. The simulation results show that, per $x=0.5$, the maximum transconductance in the with-effective mass (EM) state is $G_{m,max}=2.3$ mS/$\mu$m, which is reduced by 8% compared to the without-EM state. The JL-Ga${}_{0.5}$In${}_{0.5}$As/GaAs device in the with-EM state has the unity gain cutoff frequency of $f_T=900$ GHz, minimum noise figure of $N_{f,min}=0.29$ db, and available associated gain of $G_{\mathrm{\text{ass}}}=23.84$ db. The $f_T$ and $G_{\mathrm{\text{ass}}}$ parameters in the with-EM state decreased by 10% and 38%, respectively, compared to the without-EM state. Moreover, $N_{f,min}$ in the with-EM state increased by 65% compared to the without-EM state. Our simulation results indicated that an increase in electron effective mass with the increased $x$ can limit the analog/RF frequency and high-frequency noise performance of the JL-Ga${}_x$In${}_{1-x}$As/GaAs device.

A versatile low-voltage CMOS circuit with a trapezoidal transconductance characteristic and independently programmable slope, height and horizontal position is designed in 0.18$\mu$m standard CMOS technology. The proposed circuit is constructed from combination of two linearization methods to enhance the linearity in low voltage applications. A $-$118dB THD was obtained for a 400mV peak to peak differential input voltage at 125KHz. Simulation results using HSPICE that verify the functionality of circuit with 1.5V supply are presented. The total power consumption is only 120$\mu$W. The circuit can find application in the implementation of membership functions in analogue and mixed-signal neuro-fuzzy systems.

In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded. Simulation results are presented using 90 nm CMOS technology which show 1,800% increment in GBW and a 33.2 dB DC gain improvement in the approximately same power consumption compared to the conventional FC amplifier.

Presented work deals with applications of the single $z$-copy controlled-gain voltage differencing current conveyor (ZC-CG-VDCC) in single purpose and multifunctional biquadratic voltage- and current-mode active resistor-less filters. Electronically adjustable features of the active device (intrinsic current input resistance $R_x$, current gain $B$ and transconductance $g_m$) are controlled by DC bias current. These mentioned adjustable features allow interesting possibilities of control of the pole frequency and quality factor. Four voltage-mode solutions realizing low-pass, band-pass, high-pass and band-reject filtering solutions were designed together with two current-mode filters. The current-mode solutions have curious multifunctional capability based on full utilization of electronically controllable parameters of the ZC-CG-VDCC. Two adjustable parameters of the ZC-CG-VDCC (intrinsic current input resistance and transconductance) are used for electronic setting of features of the filter (pole frequency, quality factor, tuning). Control of the third adjustable parameter (current gain) causes reconnection-less change of the transfer function between iAP (inverting all-pass response) and iBR (inverting band-reject responses). Simulation results in PSPICE and Cadence CDS 6 are used to show characteristics of the proposed circuits.

This paper presents a supper class-AB adaptive biasing bulk-driven amplifier for ultra-low-power applications. In the proposed structure, two bulk-driven flipped voltage follower (FVF) cells are reconfigured as nonlinear tail currents using quasi-floating gate method to enhance transconductance and slew rate. In addition, two idle current controllers are employed as common source amplifiers to provide a supper class-AB structure without increasing total current consumption. The proposed structure is simulated in 0.18-$\mu$m CMOS technology at 0.5V supply with 35nW power budget. The results show a 57.9dB DC gain, 8.8kHz gain bandwidth and 38.2V/ms slew rate for the proposed amplifier.

In this paper, two highly linear OTAs are presented using a combination of three linearization techniques: floating gate, bulk driven, and source degeneration. In the first OTA, bulk driven floating gate MOSFETs are used as input transistors. The input signal given at the bulk terminals of these input transistors are in the opposite phase of the input signal provided to one of the gates of the respective floating gate MOSFET. This cross-coupling method resulted in a highly linear voltage-to-current conversion at the cost of reduced transconductance. In the second proposed OTA, this reduction in transconductance is restored by using novel quasi-bulk floating gate MOSFETs as input transistors while maintaining the improved linearity. Both the OTAs are designed and simulated using 180 nm CMOS design library and powered with $\pm$0.5V dual power supply. The process variation and mismatch effects on both the OTAs are examined using corner and Monte Carlo analysis. The layouts of the proposed OTAs are also presented and workability is confirmed using post-layout simulations.

Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ($g_m$) is the main dominant source of frequency and gain ($K_{\mathrm{\text{VCO}}}$) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates $\approx 3$ times variation in $K_{\mathrm{\text{VCO}}}$ across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5GHz is developed in 65nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum $K_{\mathrm{\text{VCO}}}$ variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4mW power from 1V power supply.

A compact memristor emulator structure using ten CMOS transistors-based structures is presented with a fully floating circuit configuration. Along with the use of such a compact CMOS structure to form a transconductance cell, the circuit requires only a single grounded capacitance and two external MOS transistors. Unlike several externally employed transconductance cells-based memristor emulators reported previously, the proposed circuit can be considered a compact architecture due to the non-employment of any external multiplier and floating passive elements, and also a lesser number of used transistors. The electronic tunability and wide-band operating frequency range (400Hz–50MHz) are the other attractive features of the proposed emulator. The circuit has been tested by performing simulations using PSPICE with 0.18$\mu$m CMOS technology. The presented simulation results clearly show the ideal non-volatile nature found in the realized memristor, which has also been employed in a neuron circuit based on the proposed emulator depicted in the article. The neuron circuit has been used to generate a spike output by applying a post-synaptic signal equivalent DC input. Finally, the circuit idea of the proposed memristor emulator has been tested by using commercial IC LM13700.

In this paper, electronic implementation of fractional-order Rössler system using operational transconductance amplifiers (OTAs) is presented which until now was only being investigated through numerical simulations. The realization offers the benefits of low-voltage implementation, integrability and electronic tunability. In addition, the proposed circuit is a MOS only design (as no BJTs have been used) which contains only grounded components and is therefore suitable for monolithic VLSI design. The chaotic behavior of the fractional-order Rössler system in consideration with the incommensurate orders has been demonstrated which finds many applications in several fields. The theoretical predictions of the proposed implementation have been verified through experimentation and HSPICE simulator using Austrian Micro System (AMS) 0.35$\mu$m CMOS process and the obtained results have been found in good agreement with the Matlab simulink theoretical results obtained using FOMCON simulink toolbox. Besides, a secure message communication system has been considered to demonstrate fully the usefulness of the chaotic system.

This paper deals with the performance of both gate and drain control coefficients to analyze the behavior of carbon nanotube field effect transistors (CNTFETs) under ballistic conditions and based on the change of different parameter value, such as oxide thickness of structure and temperature variation. A thorough study of both gate and drain control coefficient effects on the performance of CNTFETs has been conducted under different temperature and oxide layers and the output of the device has been analyzed through different parameters. Higher values of control coefficient help to attain larger transconductance by the increasing temperatures. For a fixed value of control coefficient, 4nm thickness of oxide has a transconductance of $\sim$ 4.5 $\times$ 10${}^{-5}$ S/m. Smaller oxide layer thickness has higher slope of increment in transconductance value. ON-state current to leakage current ratio shows a steady state response toward increment of gate control coefficient. Also, increment of oxide thickness has an adverse effect on current ratio, while a linear decay of current ratio is observed with the increased value of drain controlled one. Drain-induced battery lowering (DIBL) effect decreases with the value of gate control one and increases with the drain control coefficient. In this way, the optimum value for both the control coefficients has to be considered in order to perform well.

This paper presents a systematic investigation of high-temperature transport characteristics of a single nanowire Gallium Nitride nanowire field-effect transistor (GaN-NWFET) ranging from room temperature to as high as $350^{\circ }$C for the first time. The GaN-NWFET demonstrated a very good on/off current ratio ($I_{\mathrm{\text{on}}}∕I_{\mathrm{\text{off}}})$ of $3\times 10^3$ for the p-side and $2.5\times 10^3$ for the n-side at room temperature and considerably well at high temperatures. In fact, the device exhibited an on/off current ratio of $5.5\times 10^2$ and a transconductance value of $0.96\mu$S for the p-side at $350^{\circ }$C indicating a good gating effect even at high temperatures. Additionally, the device exhibited very high mobilities with the hole mobility of $3.26\times 10^3$cm²/V. s and electron mobility of $3.14\times 10^3$ cm²/V. s at room temperature. Furthermore, the device showed very high transconductance values of $0.92\mu$S and $20.3\mu$S at the temperatures of $25^{\circ }$C and $250^{\circ }$C, respectively. As a consequence, the GaN-NWFET devices could find much use not only in high-power, but also in low-power transistor applications beyond the ambient temperature $\mathrm{\text{range}}(>300^{\circ }$C) of silicon and silicon-on-insulator technologies for electronic and photonic circuits.

Nanotube structures are unprecedented in their stability and current-carrying capacity at intense driving fields. A comprehensive understanding of electron conduction from equilibrium through to the high-driving-field regime is needed. We present a microscopically conserving quantum-kinetic description of transport for ohmically contacted carbon nanotubes. The approach is computationally straightforward and can describe nonequilibrium response over a wide range of parameters. We have analyzed the interplay of degeneracy and scattering dynamics on gate-controlled conduction in the one-dimensional channel, and have determined transconductances.