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Scalable models for both active and passive components are essential for the design of highly integrated fiber–optic physical layer ICs. This paper focuses on the various technology options available of 10 Gb/s and 40 Gb/s applications, on how their constituent components are modeled and what the characteristics and requirements are for the basic building blocks. As part of the technology comparison, an overview of the performance of leading edge Si CMOS, SiGe BiCMOS and III–V technologies is presented. Scalable models for SiGe HBTs and GaAs p–HEMTs are then compared with measured data for various device sizes. Inductors, varactors, transmission lines and isolation techniques on Si and III–V substrates are discussed next followed by technology–specific implementations of VCO and digital building blacks. Finally, Transimpedance Limiting Amplifier (TIALA) as well as laser and modulator driver designs in SiGe BiCMOS, InP HBT and GaAs p–HEMT processes using scalable device models are illustrated for 10 and 40 Gb/s fiber-optics applications.

Using a 0.2-μm self-aligned epitaxial-growth silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology, we have developed a chipset for 40-Gb/s time-division multiplexing optical transmission systems. In this paper, we describe seven analog and digital ICs: a 45-GHz bandwidth transimpedance amplifier, a 48.7-GHz bandwidth automatic-gain-controllable amplifier, a 40-Gb/s decision circuit, a 40-Gb/s full-wave rectifier, a 40-Gb/s limiting amplifier with a 32-dB gain, a 45-Gb/s 1:4 demultiplexer, and a 45-Gb/s 4:1 multiplexer. To increase bandwidth of the transimpedance amplifier, a common-base input stage is introduced. In order to have high gain and wide bandwidth simultaneously, active load circuits composed of a differential transimpedance amplifier are used for the AGC amplifier, the limiting amplifier, and the decision circuit. Full-rate clocking is employed to reduce the influence caused by clock-duty variation in digital circuits such as the decision circuit, the demultiplexer, and the multiplexer. All ICs were characterized by using on-wafer probes, and some of them were built in brass-packages for bit-error rate measurement.

A 2.5 Gbps transimpedance amplifier (TIA) with the feedback resistance self-adaptively adjusted is designed for the application of optical receivers in passive optical network and implemented in Global Foundries (GF) 0.18 $\mu$m CMOS standard process. The main structure of the circuit consists of an improved three-stage current multiplexing push-pull inverter. With the diode-connected-transistor placed at each end of the inverter, the extra pole will be pulled away in order to increase the stability of the loop system. The feedback resistance of TIA is connected in parallel with the NMOS transistor, and the gate voltage of the tube is adjusted automatically to control the resistance value of this parallel structure in order to overcome the defect of the inverter which will work in the linear region on the condition of excessive optical power. A low-dropout linear regulator (LDO) is adopted from the power supply to the TIA to isolate power supply noise. The measured results demonstrate that the fabricated TIA with a photodetector capacitance of 3.2 pF has a transimpedance gain of 41.64 dB$\mathrm{\Omega }$ with a current signal frequency of 2.5 Gbit/s, and a −3 dB bandwidth of 2.35 GHz. The average input-referred noise current spectral density within the bandwidth is185 pA/Hz${}^{1/2}$, signal rise time is 195 ps, fall time is 227 ps, eye diagram height is 28 mV, optical sensitivity is −30.6 dBm, and power consumption is only 52 mW at 3.3 V power supply voltage, the chip area is $0.22\times 0.3$ mm².

This paper presents the development of a bandwidth enhancement technique for a resistive shunt-feedback transimpedance amplifier (TIA). The technique relies upon a π-peaking network realization using the shunt-feedback TIA as a part of the network in order to achieve a high bandwidth while maintaining a low noise performance. The output is obtained by making use of subsequent amplifier stages with the non-uniform constant-k output network for simultaneously high gain and bandwidth. Practical performance verification was provided via the designs and simulations of two π-peaking TIAs in a silicon CMOS implementation and a discrete HJFET implementation. Simulated results clearly indicates superior bandwidth of the π-peaking TIA over the conventional shunt-feedback TIA at practically no cost to circuit complexity and power consumption.

In this paper, a low-power structure as an inverter-base circuit is reported for broadband applications. The focus in this study is in obtaining a low-power structure. By applying cascoded structure to an inverter as a feedforward network in the structure, the DC current and hence the power dissipation are decreased. Also, by adding a two-stage active feedback, which yields no miller capacitance, to the cascoded inverter, the structure of the TIA is completed. Simulation results in HSPICE using 90nm CMOS technology parameters show 41dB$\mathrm{\Omega }$ transimpedance gain, 6.5GHz frequency bandwidth and 2.7$\mu$Arms input referred noise, which consumes only 1.67mw power at 1V supply. Results and analysis indicate that the proposed TIA is suitable to work as a low-power 10 Gbps transimpedance amplifier in an optical receiver.

In this paper, a study of noise reduction of an electrochemical sensor is presented. This study is initiated based on the fact that the signal from the electrochemical sensor has quite high noise. The current signal from the sensor is very weak and noisy due to high impedance and complex process on the sensor and measured media such as a solution of dissolved oxygen. The current is usually converted using a transimpedance amplifier with high voltage-to-current ratio by a feedback resistance, which usually also produces large noise due to high feedback resistance value. This will contribute to an additional noise to the natural noise of the sensor and measured media, causing more noisy result. A modified transimpedance amplifier is proposed to reduce the noise from the sensor and converter to increase signal-to-noise ratio. The modification employs a current compensation, so that the current noise is suppressed at the converter input. The noise and signal measurements at the output of the compensated transimpedance amplifier show noise reduction compared to the standard transimpedance amplifier and measurement error reduction of the measured dissolved oxygen down to 0.89%.

Scalable models for both active and passive components are essential for the design of highly integrated fiber–optic physical layer ICs. This paper focuses on the various technology options available for 10 Gb/s and 40 Gb/s applications, on how their constituent components are modeled and what the characteristics and requirements are for the basic building blocks. As part of the technology comparison, an overview of the performance of leading edge Si CMOS, SiGe BiCMOS and III–V technologies is presented. Scalable models for SiGe HBTs and GaAsp–HEMTs are then compared with measured data for various device sizes. Inductors, varactors, transmission lines and isolation techniques on Si and III–V substrates are discussed next followed by technology–specific implementations of VCO and digital building blocks. Finally, Transimpedance Limiting Amplifier (TIALA) as well as laser and modulator driver designs in SiGe BiCMOS, InP HBT and GaAs p–HEMT processes using scalable device models are illustrated for 10 and 40 Gb/s fiber-optics applications.

Using a 0.2-μm self-aligned epitaxial-growth silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology, we have developed a chipset for 40-Gb/s time-division multiplexing optical transmission systems. In this paper, we describe seven analog and digital ICs: a 45-GHz bandwidth transimpedance amplifier, a 48.7-GHz bandwidth automatic-gain-controllable amplifier, a 40-Gb/s decision circuit, a 40-Gb/s full-wave rectifier, a 40-Gb/s limiting amplifier with a 32-dB gain, a 45-Gb/s 1:4 demultiplexer, and a 45-Gb/s 4:1 multiplexer. To increase bandwidth of the transimpedance amplifier, a common-base input stage is introduced. In order to have high gain and wide bandwidth simultaneously, active load circuits composed of a differential transimpedance amplifier are used for the AGC amplifier, the limiting amplifier, and the decision circuit. Full-rate clocking is employed to reduce the influence caused by clock-duty variation in digital circuits such as the decision circuit, the demultiplexer, and the multiplexer. All ICs were characterized by using on-wafer probes, and some of them were built in brass-packages for bit-error rate measurement.