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The Inverse Discrete Cosine Transform (IDCT) is an important function in HDTV, digital TV and multimedia systems complying with JPEG or MPEG standards for video compression. However, the IDCT is computationally intensive and therefore very expensive to implement in VLSI using direct matrix multiplication. By properly arranging the input coefficient sequence and the output data, the rows and columns of the transform matrix can be reordered to build modular regularity suitable for custom implementation in VLSI. This regularity can be exploited, so that a single permutation can be used to derive each output column from the previous one using a circular shift of an accumulator’s input data multiplied in a special sequence. This technique, using only one 1-dimensional IDCT processor and seven constant multipliers, and its implementation are presented. Operation of 58 MHz under worst case conditions is easily achieved, thus making the design applicable to a wide range of video and real time image processing applications. Fabricated in 0.5 micron triple metal CMOS technology, the IDCT contains 70,000 transistors occupying 7 mm² square silicon. The design has been used on an AT&T MPEG video decoder chip.

This paper describes some issues in building a 3-D human face modeling system which mainly consists of three parts:

• Modeling human faces;

• Analyzing facial motions;

• Synthesizing facial expressions.

A variety of techniques developed for this system are described in detail in this paper. Some preliminary results of applying this system to computer animation, video sequence compression and human face recognition are also shown.

The sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71–90.01% of area cost and improves the macroblock (MB) processing speed between 1.7–8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.

This paper reviews recent state-of-the-art H.264 sub-pixel motion estimation (SME) algorithms and architectures. First, H.264 SME is analyzed and the impact of its functionalities on coding performance is investigated. Then, design space of SME algorithms is explored representing design problems, approaches, and recent advanced algorithms. Besides, design challenges and strategies of SME hardware architectures are discussed and promising architectures are surveyed. Further perspectives and future prospects are also presented to highlight emerging trends and outlook of SME designs.

Motion estimation (ME) is a highly computationally intensive operation in video compression. Efficient ME architectures are proposed in the literature. This paper presents an efficient low computational complexity systolic architecture for full search block matching ME (FSBME) algorithm. The proposed architecture is based on one-bit transform-based full search (FS) algorithm. The proposed ME hardware architectures perform FS ME for four macroblocks (MBs) in parallel. The proposed hardware architecture is implemented in VHDL. The FSBME hardware consumes 34% of the slices in a Xilinx Vertex XC6vlx240T FPGA device with a maximum frequency of 133MHz and is capable of processing full high definition (HD) ($1920\times 1080$) frames at a rate of 60 frames per second.

Video compression technologies have recently become an integral part of the way we create, communicate and consume visual information. The aim of this Letter is to show that the Cellular Neural Network (CNN) paradigm can be exploited for obtaining accurate video compression. In particular, the Letter presents an architecture that combines CNN algorithms and H.264 codec. The compression capabilities of the devised coding system are analyzed in detail using some benchmark video sequences, and comparisons are carried out between the CNN-based approach and the H.264 codec working alone. The outcome of the analysis is that the CNN-based coding approach outperforms the H.264 codec working alone, allowing to perceive the capabilities of the CNN paradigm.

Motion compensation using deformable triangle patches has been successfully used for low bit rate coding of videophone sequences. They were also shown to be particularly efficient for interframe coding of MRI sequences, for which the difference between image slices can be well modeled by locally affine deformations. Regular triangular meshes were used in previous works. In this paper, we present a quadtree decomposition algorithm to generate a triangle mesh for which smaller triangles are used in image areas where the motion or deformation is more complex. Grid points are recursively added to areas where the reduction in prediction error is more significant. Results show that using variable size triangular patches increases the PSNR of the motion-compensated image while reducing the number of grid points when compared to a regular triangular mesh.

Video compression techniques have been applied routinely in order to conserve storage space and minimize bandwidth utilization in various video applications. To reduce inter-pixel redundancies inside and between video frames, video codecs (coder/decoder or compression/decompression) are mainly characterized by applying motion estimation and motion compensation (MEMC) in combination with discrete cosine transform (DCT). However, blocking artifacts are obvious from the block-based motion estimation and transformation, especially at low bit rates. Due to the intrinsic advantages of multiresolution and scalability of discrete wavelet transform (DWT), video compression techniques have been infused with exciting prospects by the beneficial integration of motion estimation and wavelet transformation. The contributions of this paper are in (1) proposing a design architecture of the wavelet-domain encoder and decoder; (2) implementing the multiresolution motion estimation and compensation method; and in (3) realizing the dynamic entropy encoding and decoding, so as to achieve more efficient video compression than the conventional spatial domain methods for low bit rate applications without the annoying blocking artifacts.

When the embedded zerotree wavelet (EZW) algorithm was first introduced by Shapiro, four types of symbols (zerotree (ZTR), isolated zero (IZ), positive (POS), and negative (NEG)) were used to represent the tree structure. An improved version of EZW, the set partitioning in hierarchical trees (SPIHT) algorithm was later proposed by Said and Pearlman. SPIHT removed the ZTR symbol, while keeping the other three symbols in a slightly different form. In the SPIHT algorithm, the coding of the parent node is isolated from the coding of its descendants in the tree structure. Therefore, it is no longer possible to encode the parent and its descendants with a single symbol. When both the parent and its descendants are insignificant (forming a degree-0 zerotree (ZTR)), it cannot be represented using a ZTR symbol. From our observation, the number of degree-0 ZTRs can occur very frequently not only in natural and synthesis images, but also in video sequences. Hence, the ZTR symbol is reintroduced into SPIHT in our proposed SPIHT-ZTR algorithm. In order to achieve this, the order of sending the output bits was modified to accommodate the use of ZTR symbol. Moreover, the significant offspring were also encoded using a slightly different method to further enhance the performance. The SPIHT-ZTR algorithm was evaluated on images and video sequences. From the simulation results, the performance of binary-uncoded SPIHT-ZTR is higher than binary-uncoded SPIHT and close to SPIHT with adaptive arithmetic coding.

This paper proposes a compression algorithm using octonary repetition tree (ORT) based on run length encoding (RLE). Generally, RLE is one type of lossless data compression method which has duplication problem as a major issue due to the usage of code word or flag. Hence, ORT is offered instead of using a flag or code word to overcome this issue. This method gives better performance by means of compression ratio, i.e. 99.75%. But, the functioning of ORT is not good in terms of compression speed. For that reason, physical- next generation secure computing (PHY-NGSC) is hybridized with ORT to raise the compression speed. It uses an MPI-open MP programming paradigm on ORT to improve the compression speed of encoder. The planned work achieves multiple levels of parallelism within an image such as MPI and open MP for parallelism across a group of pictures level and slice level, respectively. At the same time, wide range of data compression like multimedia, executive files and documents are possible in the proposed method. The performance of the proposed work is compared with other methods like accordian RLE, context adaptive variable length coding (CAVLC) and context-based arithmetic coding (CBAC) through the implementation in Matlab working platform.

A low-complexity wavelet-based video coding technique is proposed which adopts JPEG-2000 image coding. The wavelet transformation and subband quantization are developed and optimized in order to reduce the ringing artifacts especially at very low bit rate. The proposed coding technique reduces the coding complexity and performs well at average PSNR. As compared to other rival coding methods the proposed coding policy has a good compression ratio and an improved visual quality.

In this paper, we propose a novel motion compensated prediction of visual object by transforming its edge map under the geometrical constraints due to perspective effects and generating the current object texture by linear interpolation. Experimental results show that it gives precise reconstruction.

This paper describes some issues in building a 3-D human face modeling system which mainly consists of three parts:

• Modeling human faces;

• Analyzing facial motions;

• Synthesizing facial expressions.

A variety of techniques developed for this system are described in detail in this paper. Some preliminary results of applying this system to computer animation, video sequence compression and human face recognition are also shown.

The Inverse Discrete Cosine Transform (IDCT) is an important function in HDTV, digital TV and multimedia systems complying with JPEG or MPEG standards for video compression. However, the IDCT is computationally intensive and therefore very expensive to implement in VLSI using direct matrix multiplication. By properly arranging the input coefficient sequence and the output data, the rows and columns of the transform matrix can be reordered to build modular regularity suitable for custom implementation in VLSI. This regularity can be exploited, so that a single permutation can be used to derive each output column from the previous one using a circular shift of an accumulator's input data multiplied in a special sequence. This technique, using only one 1-dimensional IDCT processor and seven constant multipliers, and its implementation are presented. Operation of 58 MHz under worst case conditions is easily achieved, thus making the design applicable to a wide range of video and real time image processing applications. Fabricated in 0.5 micron triple metal CMOS technology, the IDCT contains 70,000 transistors occupying 7 mm² square silicon. The design has been used on an AT&T MPEG video decoder chip.