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This paper presents two novel Floating Current Source (FCS)-based CMOS negative second generation current conveyor (CCII-) realizations suitable for very large scale implementation. The proposed realizations provide high voltage and current tracking accuracy, as well as large voltage and current transfer bandwidths. Simulation results show that the first proposed wide-band CCII- bandwidth is about 972 MHz. Targeting low-power dissipation, a second low-power version of the wide-band CCII- is proposed at the expense of lower bandwidth and accuracy. The proposed CCII- realizations are layout-friendly because they can be easily fabricated in a systematic modular layout fashion. In addition, a fair comparison is held between the proposed realizations and the only FCS-based CCII- realizations in the literature to show the strength of the proposed circuits. The proposed two CCII- realizations show excellent immunity to process variations and transistor mismatch. In addition, they are insensitive to the temperature variations. Finally, two common CCII- applications are presented.

This paper presents a low-power, high gain-bandwidth product (GBW) gain cell for gigabits-per-second communications. Based on this gain cell, a large GBW limiting amplifier (LA) and two types of high oscillation-frequency ring oscillators (ROs) are implemented with good energy efficiencies. Fabricated in the 0.18$\mu$m CMOS process, the proposed LA can support 1.25Gbps data-rate with a measured GBW of 338GHz under 5mW. The proposed single- and multi-loop ROs obtain a simulated typical oscillation frequency of 5.26GHz and 6.96GHz, respectively, under 6.2 mW, which is less than one-eighth the power consumption of published ROs at similar frequencies in the same process.

In this paper, a wideband full-360^o phase shifter with 6 bits of accuracy has been designed and simulated with minimal root mean square (RMS) phase error. The proposed phase shifter deployed a feed forward path including a frequency-to-voltage converter (FVC) to minimize the mismatch in quadrature generation to eventually reduce the RMS phase error for S-band (2–4GHz) applications. The designed phase shifter in 180nm CMOS technology achieves an RMS phase error in the range of 0.607–1.18^∘ with $-50$dBm input signal over 2–4GHz frequency band. With lower input signal of $-75$dBm, the RMS phase error is 0.621–1.34^∘ for 2–4GHz input frequency. The proposed phase shifter shows an RMS amplitude error less than 0.41dB over 2–4GHz frequency. The 1-dB compression point ($P_{-1\mathrm{\text{dB}},\mathrm{\text{CP}}}$) of the proposed phase shifter is $-23$dBm. The proposed wideband phase shifter draws 32 mA from 1.8 supply voltage. It occupies an active area of only 0.025mm², due to active design without any inductor.