This paper proposes a well-optimized FPGA implementation of a chaos-based cryptosystem for real-time image encryption and decryption. A highly sensitive Pseudo-Random Number Generator (PRNG) based on the Lorenz chaotic system is designed to generate pseudo-random numbers. A high-quality encryption key is acquired by encrypting the numbers of a 128-bit counter using the PRNG. For image encryption, the image is first decomposed into 128-bit blocks. Then, the blocks are encrypted by XORing pixels with the key stream. R cycles of encryption can be achieved to increase complexity. Finally, the blocks are concatenated to form an encrypted image. The algorithm is designed, implemented, and validated on the Xilinx Zynq FPGA platform using the Vivado/System Generator tool. The hardware design is well optimized for pipeline processing and low resource utilization. The experimental synthesis indicates that the provided architecture achieves high performance in terms of frequency and throughput. The encryption scheme is evaluated and analyzed by several tools and tests using different images. The experimental simulation results demonstrate that the hardware implementation is faster than a software implementation while maintaining the technique’s effectiveness. The proposed hardware implementation is extremely adopted for secret image encryption and decryption that can be used in real-time applications.
