Narrow Results

We present an unified explanation of the transconductance-to-drain current (g_m/I_D)-based noise analysis in this paper. We show that both thermal noise coefficient (γ) and device noise corner frequency (f_co) are dependent on the g_m/I_D of a transistor. We derive expressions to demonstrate the relationship between the normalized noise power spectral density technique and the technique based on γ and f_co. We conclude this letter with examples to demonstrate the practical implication of our study. Our results show that while both techniques discussed in this letter can be used to compute noise numerically, using γ and f_co to separate thermal noise from flicker noise provides additional insight for optimizing noise.

A design flow using the $g_{\text{m}}$/$I_{\text{D}}$ methodology with the adaptive particle swarm optimization (PSO) algorithm is proposed for the modern analog circuit in this paper. For the advanced CMOS process, $g_{\text{m}}$/$I_{\text{D}}$ methodology is suitable to the long channel and short channel design in all transistor operation regions. Different from the classical PSO algorithm, the adaptive PSO algorithm features the better search efficiency and faster convergence speed over the global search. Two amplifiers were designed and implemented in a standard 0.11$\mu$m CMOS process using MATLAB and HSPICE. Using the thermal noise coefficient $\gamma$ and the corner frequency $f_{\text{corner}}$, this paper explored the noise design budget of low-power multistage amplifier in different saturation modes. Detailed optimization of the objective function and constraints are classified into the mono-objective case and the multi-objective case. The total running times of simulations are 5649 s and 6813 s while the errors are less than 9% and 10%, respectively. Compared with CODE, GA$+$PF and DE$+$PF algorithms, it can save more running time and improve the accuracy of the design. Moreover, it provides more design freedom for the trade-off among gain, the gain-bandwidth (GBW) product, noise and the phase margin under worst cases without extra tweaking. Not only can the methodology work in the 0.18$\mu$m CMOS process, but also be migrated to the 0.11$\mu$m CMOS process, even in the nanometer analog circuit.