International Journal of High Speed Computing

The difficulties in conceptualizing the interactions among a large number of processors make it difficult both to identify the sources of inefficiencies and to determine how a parallel program could be made more efficient. This paper describes an instrumentation system that can trace the execution of distributed memory parallel programs by recording the occurrence of parallel program events. The resulting event traces can be used to compile summary statistics that provide a global view of program performance. In addition, visualization tools permit the graphic display of event traces. Visual presentation of performance data is particularly useful, indeed, necessary for large-scale parallel computers; the enormous volume of performance data mandates visual display.

To understand the system interdependencies of a multiprocessor and the effects of these interdependencies on parallel applications, it is necessary to include a performance monitoring facility in the multiprocessor system. Such a monitoring facility can be either transparent (i.e. requiring no user initiated intervention) or non-transparent. In this paper we describe the performance monitoring facilities that are available to the user of the RP3 system. We will also describe our initial experience using these facilities and demonstrate their functionality.

This paper presents a modeling methodology devoted to the performance evaluation of parallel architectures. The methodology is based on the decomposition of the modeling process into seven stages. In each stage specific techniques, appropriate to parallel architectures, are applied, such as aggregation methods, a thorough distinction between the architecture model and the application program model, the constitution of program classes using data analysis techniques. The methodology is then illustrated through a case study, the loosely Coupled Array of Processors (lCAP) system, designed at IBM Kingston. Use of the lCAP model allows to predict the performance of the lCAP system, in terms of response time, resource utilization, waiting times, and to investigate many alternatives with regard to the system configuration (e. g. number of system components, component interconnection scheme, component characteristics), or to the parallel program structure (e. g. parallel task granularity, load imbalance).

This paper presents the results of a study conducted to evaluate the inherent memory reference behavior of several engineering/scientific applications, executing on shared memory, MIN-based, parallel systems. In this study, system sizes of two to 64 processors were evaluated. A trace-driven simulation model was used to obtain dynamic reference characteristics of the code. Included in this code were explicit declarations of shared variables. Our results indicate that a significant amount of explicitly declared shared data is accessed as either readonly by several processors, or read-write by a single processor. Furthermore, lines containing synchronization variables tend to see small ownership times at a processor and are accessed by several processors in the system. We also note that, as expected, relatively more references are to data with smaller ownership times, as the number of processors increase. Finally, the application data set size can have an impact on ownership time, as the number of processors increase.