International Journal of High Speed Computing

We present a new, rapid, and easily parallelized finite difference method for computing fourth-order accurate solutions of Poisson's equation, Δu=f, on irregular regions. This method is a generalization of a method due to Qun and Tao for obtaining fourth-order accurate solutions of Poisson's equation on rectangular regions by forming a linear combination of two second-order accurate solutions obtained by calculations with different stencils.

In our method we first embed the irregular region in a larger rectangular region and define a discontinuous extension. Using a method we presented previously, we could compute two second-order accurate approximations using the same two second-order accurate stencils as Qun and Tao did. However, because the functions we compute, and therefore the truncation errors, are discontinuous, taking the same linear combination of the two solutions will not provide a fourth-order accurate solution. We show how one can correct for these discontinuities in truncation error by local computations, and how one can obtain a fourth-order accurate solution. We also provide results of numerical experiments.

The Broadcasting with Selective Reduction (BSR) model of parallel computation is applied to the problem of finding Maximal Sum Subsegments in one-dimensional sequences of n elements, and to the related problem of Maximal Sum Subrectangles in two-dimensional arrays. The one-dimensional case is shown to be solvable in constant time using O(n)BSR processors. The two-dimensional case is solved in constant time with O(n³)BSR processors (for an n×n array).

The Quantum Flux Parametron (QFP) is a Josephson Junction device using the polarity of a quantum magnetic flux to represent a binary information. A quantum unit of magnetic flux in a QFP can be controlled to realize majority logic operation, consequently AND and OR logics can be realized. Together with negation, which can be realized by a flux-inverting transformer, various computing logic devices can be constructed. In addition, the QFP is also a latching device so that a flux can be confined in the device to realize memory function. Due to the homogenous nature of memory and logic circuits as well as the flux nature of the signal which can be transmitted inductively, an entirely new Josephson supercomputer with memory and CPU pipelining arranged in a 3D setting was conceived. The computer with 40 processors is expected to run at a maximum speed of 20 GFLOPS of scalar processing.

In recent years, there has been a trend towards multiple instruction stream computer architectures. The Cyclic Pipeline Computer (CPC) is an early example of a statically scheduled multiple instruction stream computer. It shares its pipeline among multiple instruction streams in a time-shared manner. The advantages of such machines are that they are capable of hiding latencies, in particular memory access latencies. However, if these instruction streams share a common cache, the cache behavior is adversely affected because the memory access pattern is not characterized by one working set, but by a combination of working sets. In this paper, we will examine the effects of multiple instruction stream execution on the cache miss ratio. While a direct mapped cache might be sufficient for a single instruction stream, our results indicate that this is not true for multiple instruction stream execution. We also found that the set mapping function plays an important role in getting adequate hashing in multiple instruction stream execution.