International Journal of High Speed Computing

A Distributed Computing System (DCS) comprising networked heterogeneous processors requires efficient tasks to processor allocation to achieve minimum turnaround time and highest possible throughput. Task allocation in DCS remains an important and relevant problem attracting the attention of researchers in the discipline. A good number of task allocation algorithms have been proposed in the literature [3–9]. This algorithm considered allocation of the modules of a single task to various processing nodes and aim to minimize the turnaround time of the given task. But they did not consider execution of modules belonging to various different tasks (i.e. multiple tasks). In this work we have considered the number of modules that can be accepted by individual processing nodes along with their memory capacities and arrival of multiple disjoint tasks to the DCS from time to time. In this paper, a method based on genetic algorithm is developed which is memory efficient and give an optimal solution of the problem. The given simulation results also show significant achievement in this regard.

Real-time messages, which have user defined end-to-end delay requirements, can be delivered using a real-time communication method. This paper proposes two path selection algorithms for real-time communication and conducts a simulation study to evaluate these two algorithms. On the basis of this simulation study, it can be seen that, for effective real-time communication, it is important to consider the number of hops utilized by each path and the link utilization of all effected links. In particular, the number of hops required for each path was found to be the most important factor. The proposed path selection algorithms are found to perform as well or better than previously proposed algorithms while using fewer network resources.

The linked-based cache coherence protocols, such as the IEEE Scalable Coherence Interface (SCI), have been widely implemented in current highly scalable multiprocessor systems. Thus, we propose several enhanced linked-based cache coherence protocols in multiprocessor systems to evaluate their performance. However, migratory sharing data references in the linked-based systems still incur many cache misses that can be reduced by merging the invalidation/update requests and the cache misses. Research has been devoted to optimizing the migratory sharing references for the centralized directory coherence protocols, but their mechanisms cannot support the linked-based cache coherence protocols. This paper presents enhanced SCI protocols with an effective hardware technique to reduce the overhead of migratory sharing references for the linked-based cache coherence protocols. It reduces cost by eliminating some of the unnecessary supporting mechanisms in centralized directory protocols. The simulation results in SPLASH benchmarks show that our hardware methods enhanced the system performance by up to an average of 10%, by reducing the overhead of the migratory sharing references. The extra benefit of our mechanism is the elimination of the false sharing overhead by degrading a block to shared mode again.