International Journal of High Speed Electronics and Systems

Study of two-photon absorption (TPA) has been carried out for all-optical logic operation based on quantum-dot semiconductor optical amplifier (QD-SOA). XOR gate, AND gate and pseudo-random bit sequence (PRBS) were all modeled with the TPA effect on the existing rate equation. Inclusion of TPA induced pumping has increased the output Q-factor (quality). The output result demonstrates that the quality of the output is dependent on the input pulse width and the operation speed. The PRBS system modeled with TPA shows that it can operate at 250 Gb/s and 320 Gb/s and increase in pulse width decrease the Q-factor.

Mode locked fiber ring laser using graphene nanoparticles as saturable absorbers to compress the pulse width has been studied. An experimental method to demonstrate the generation of pulse train with 50 GHz repetition rate with an ultrashort pulse width has been demonstrated. This method uses a combination of rational harmonic mode-locking (RHML) and a saturable absorber in the fiber ring laser. The pulse width using saturable absorbers is shorter by about a factor of 2 compared to that without a saturable absorber. Pulse generation using fiber ring laser with a saturable absorber has been analyzed. The experimental results are in agreement with the results from the simulation.

This paper discusses commonly used reverse engineering methods to illegally recreate printed circuit board (PCB) designs. A solution using transformative electronics is presented to prevent the discussed reverse engineering methods by obfuscating the design. The transformative electronics solution is employed in a specific application that results in a reverse engineered board to be incorrectly recreated, where the signals would be distorted due to added electromagnetic interference (EMI). The non-conductive vias that are part of the obfuscation would allow the inclusion of EMI generators that would not affect the circuit in an original design but would prevent copied designs from working correctly. A machine learning algorithm is being designed to optimize the placement of the EMI sources in an original PCB.

Volatile organic compounds (VOCs) are important biomarkers in exhaled breath or skin secretion of patients under various medical or pre-medical conditions. As such, VOCs have been explored as alternative biomarkers in the detection of diseases, including asthma, tuberculosis, and lung cancer. In this regard, a rapid, cost-effective, facile, and sample-free strategy is advantageous and critically needed for premedical screening, medical diagnosis, and health monitoring. In this review, we present an overview of the latest progress of using nanomaterial-based chemo-resistive VOC sensors for fast, real-time, and non-invasive diagnosis of diseases via detecting VOCs from exhaled breath and other sources from human body. The origin and emission of VOCs are summarized from human body, and the VOC signatures are discussed as related to specific disease. Targeting specific VOCs, chemoresistive sensors using different nanomaterials are reviewed in terms of their sensing performance metrics including sensitivity, selectivity, response/recovery time, and stability. Various strategies for improving VOC sensor performance are discussed, specifically on the material and signal processing-based approaches.

The development of solar cells using mixed organic-inorganic perovskite materials requires the epitaxial deposition of thin films on large-area, lattice-mismatched substrates. It is therefore important to understand the effects of lattice mismatch, elastic strain, and lattice defects on device performance. In this paper, we have conducted a preliminary investigation to estimate the critical layer thickness for lattice relaxation in FAPbBr_xI_3-x alloys deposited epitaxially on KCl (001) substrates. The critical layer thickness exceeds 10 nm in the vicinity of 2.2 < x < 2.8, but is strongly dependent on x as well as growth temperature, so the achievement of stable, coherently-strained epitaxial layers will require tight control of the composition and uniformity.

Halide perovskite materials such as FAPbI3 are of great interest for photovoltaic applications and could replace silicon cells if problems of chemical instability, strain and crystal defects are solved. In this paper we present a preliminary modeling study of lattice relaxation in epitaxial FAPbI₃ on MAPbCl_xBr_3-x (001).

This paper presents the experimental characteristics of 3-state n-MOS inverters utilizing Quantum Dot Gate (QDG) FETs. By employing FETs that have quantum dots in the gate region, particularly Si-SiOx cladded quantum dots and Ge-GeOx cladded quantum dots, intermediate states were observed in both variations of the device, both of which using the same architecture and mask set.

This paper evaluates the propagation delay of a four-state/two-bit spatial wavefunction-switched field-effect transistors (SWS) FET-based inverter. The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in the upper or lower channel. A calibration method based on an analytical propagation delay model expanded for the SWS-FET based inverter to account for the multiple quantum wells within the device. Cadence iterative simulations are used for calibrating the SWS inverter size to reach a symmetrical propagation delay for the four logic transitions. The SWS transfer characteristic and the inverter circuit time specifications are obtained by integrating the BSIM (Berkeley Short-channel IGFET Model) and the Analog Behavioral Model (ABM). Calibration and adjustment of the contributing parameters of the model leads to the improvement of the device accuracy for circuit designs based on SWS-FET technology.

Power dissipation of spatial wave function switched (SWS) FETs four-state inverter is the focus of this paper. The current can flow through multiple channels in a (SWS)-FETs, which comprises vertically stacked quantum well/quantum dot channels. Using four voltage levels, the four-state SWS transistor inverter circuit is simulated. Cadence was used to perform SWS-FET inverter circuit simulations to evaluate power dissipation. To develop the SWS-FET model, an Analog Behavioral Model (ABM) and the Berkeley Short-Channel IGFET Model (BSIM4.6) were combined. To evaluate the inverter circuit’s transient behavior, a 0.18-μm technology node was used. The improvement in power dissipation, the frequency of operation, and reduction in cell area are all approximately is by a factor of 2-3. As a result, circuits based on SWS-FET inverters overcome the limitations of earlier implementations of 4-state logic circuits.

This paper presents experimental results of nMOS quantum dot gate field effect transistor (QDGFET) based inverter devices for SRAM devices. A three-state inverter device was fabricated and tested with Si/SiO₂ quantum dots. The work performed here builds off previous works performed with Si/SiO₂ dot-based inverters which used two layers of quantum dots. This research explores multi-state SRAM device operation. A three-state (Si QDs) and a four-state (Si and Ge QDs) inverter are described, and they will allow for multistate logic devices to be utilized in everyday logic chips, which will require less devices to perform the same tasks as conventional devices, double the capacity of the device, and require less power, which will generate less of a thermal footprint. The data of the Half Cell SRAM, comprised of one access transistor and an inverter along with a capacitor, is presented here.

This paper investigates the underlying physics of a SRAM device utilizing three-state Quantum Dot Gate (QDG) FETs by building up the physics from the general QDG-FET, its relation to the QDG-Inverter, and ultimately, the QDG-SRAM. The resulting equations from the exploration of the device physics were utilized to create a simulation within SIMULINK. From the simulation, it was found that in addition to being able to store the “1” and “0” states that are customary for an SRAM device, there is also the ability to store an intermediate state and a pseudo-state as a result of the intermediate state, allowing for the possibility of a 2-bit SRAM device in the same spatial constraints of a conventional SRAM unit cell. Additionally, the experimental results of the QDG-SRAM half-cell and the implications of utilizing a 4 state device to create either a 4 state SRAM cell or a 6 state SRAM cell with two pseudo-states are also discussed.

This paper presents multi-state quantum dot channel (QDC) FETs incorporating cladded quantum dots forming a novel superlattice (QDSL) as the transport channel. Harnessing QDSL mini-energy band transitions as well as the encoding of spatial location of carriers in the upper or lower quantum dot channels is utilized to obtain 8- and 16-logic states. Potentially, 32-logic states can be achieved by additionally incorporating QDSL between tunnel oxide and gate. This maybe an interim alternative to sub-milliKelvin Si/SiGe qubits.

It is well known that a solution to a second order differential equation with roots of its characteristic equation in the right half plane is unbounded. If a delay of the right magnitude is introduced into the equation the solution is bounded. This paper investigates this phenomenon by imbedding a second order differential equation with first order delay by embedding the equation in a field of equivalent classes of quotients of polynomials in the modified differential and delay operator over the real field.

Because of chip fabrication outsourcing, piracy, reverse engineering, and counterfeiting are major concerns for the semiconductor industry as well as the government. To prevent these issues, Physical Unclonable Functions (PUFs) based methods have been proposed has a way to authenticate chips. PUFs extract randomness from the manufacturing variations of a device that is probabilistic in nature. PUFs are generally easy to implement, but, because of its random behavior, its response is hard to predict and model. Many existing PUF techniques such as arbiter and ring oscillator can be hard to implement inside a chip because of their large area overhead. Hence, we have proposed a novel low pass filter PUF design in this work based on the internal resistor and capacitor variations within an IC. We have simulated the setup in Cadence Virtuoso for a 45 nm technology node. The resultant output voltage of our proposed PUF will be different at the same cut-off frequency because of the manufacturing variations. Finally, the output of the low pass filter PUF is connected with an inverter to make the signal digital and after that, a digital counter is connected with the inverter to measure the pulse width that can be used for generating a unique PUF output.

This paper presents a photogate MOS-FET device, which would function as an infrared photodetector in the 0.3-0.4 eV range involving intra-mini-energy band transitions in the GeO_x-cladded Ge quantum dot channel. Energy band density of states (DOS), mini-energy band separations for indirect as well direct bands are computed.

This paper proposes an energy efficient approach for securing inter-connecting IOT devices with servers. A scheme using blockchain and a second network for security management was previously described [1]. To overcome the drawbacks and shortcomings of using traditional smart contract with Ethereum, a new approach is proposed. The proposed approach ensures that the overall IoT network is “hardened” against attack using a framework which is environmentally sustainable and meets the stringent requirements of mission critical applications. This new approach also results in shorter latency, higher throughput and consuming less power, thus suitable for edge computing environment in mobile.

The recent developments in mmWave and Internet of Things (IoT) technologies have dramatically increased the interest and demand for radio frequency (RF) devices that can be used for applications such as smart cities, energy harvesting, and ubiquitous wireless sensor networks. Additive manufacturing technologies (AMT) plays an important role to support these applications, as they allows to significantly reduce fabrication costs and times while enabling the achievement of devices with more complex geometries and the possibility of using a wide variety of materials. This publication reviews recent developments of state-of-the-art wireless devices including reconfigurable antennas, frequency-selective surfaces and highly scalable phased arrays enabled by AMT capabilities. It also discusses the benefits of AMT in the fabrication of interconnects that are suitable for packaging of fully-integrated antennas.

The recent advance of artificial intelligence (AI) has shown remarkable success for numerous tasks, such as cloud computing, deep-learning, neural network and so on. Most of those applications rely on fast computation and large storage, which brings various challenges to the hardware platform. The hardware performance is the bottle neck to break through and therefore, there is a lot of interest in exploring new solutions for computation architecture in recent years. Compute-in-memory (CIM) has drawn attention to the researchers and it is considered as one of the most promising candidates to solve the above challenges. Computing-In-memory is an emerging technique to fulfill the fast-growing demand for high-performance data processing. This technique offers fast processing, low power and high performance by blurring the boundary between processing cores and memory units. One key aspect of CIM is performing matrix-vector multiplication (MVM) or dot product operation through intertwining of processing and memory elements. As the primary computational kernel in neural networks, dot product operation is targeted to be improved in terms of its performance. In this paper, we present the design, implementation and analysis of quantum-dot transistor (QDT) based CIM, from the multi-bit multiplier to the dot product unit, and then the in-memory computing array.

This paper presents FETs with vertically-stacked multiple quantum dot (QD) layers, comprising of GeOx cladded Ge quantum dots, serving as transport channel, floating gate in memory cell, and quantum dot gate that exhibit multi-state characteristics. The structures can be used as 8- and 16-state logic, a room-temperature alternative to sub-milliKelvin Si/SiGe qubits. In addition, they can be used as distributed NVRAMs with fast Write/Erase, SRAMs, and multi-state CMOS-X logic applications. Here, X symbolizes Multi-state CMOS compatible operations using SWS or QDC FETs or memories. The novelty includes: (i) coding of distinct states based on drain current changes in quantum dot channels via intra-sub band transitions and spatial location of carrier wavefunctions, (ii) integrating QDC-NVRAM cells with SRAM based cache, and multi-bit logic based computing.