International Journal of Nanoscience

This paper presents a detailed study of theoretical performance of graphene field effect transistor (GFET) using analytical approach. GFET shows promising performance in terms of faster saturation as well as extremely high cutoff frequency (3.9THz). A significant shift of the Dirac point as well as an asymmetrical ambipolar behavior is observed on the transfer characteristics. Similarly, an approximate symmetrical capacitance–voltage (C–V) characteristics is obtained where it has guaranteed the consistency because it shows a significant saturation both in the accumulation and inversion region. In addition, a high transconductance of 6800uS at small channel length (20nm) along with high cutoff frequency (3.9THz) has been observed which demands for high speed field effect devices.

In this work, thin lead zirconate titanate, Pb[Zr${}_{0.52}$Ti${}_{0.48}$]O₃ (PZT) films have been developed from a novel sol–gel route. The sol–gel films were deposited by spin coating method. Isopropanol-based solution was used for its less toxic property. Gold (Au), platinum (Pt) and indium tin oxide (ITO) were used as substrates. Homogeneous polycrystalline films with (110) preferred orientation were obtained from all the films. The films behaved as ferroelectric material where dielectric constant at 0V for the films obtained from Au, Pt and ITO substrates were 484, 770 and 655, respectively. The coercive field values were around 10–15KV/cm which revealed that the films were soft ferroelectric.

The ballistic performance of Si and Ge nanowire (NW) is compared in this study. Current–voltage characteristic is obtained by self-consistently solving the nonequilibrium Green’s function (NEGF) transport equation with Poisson’s equation. The result is obtained at $⟨001⟩$ channel orientation. Simulation result shows Ge NW gives higher ON-state current than Si NW, when OFF-state current is made equal by gate metal work function engineering. However, at subthreshold region, performance of NW FET for both material is almost identical. The intravalley and intervalley electron–phonon scattering effect is also calculated using the deformation potential theory and the self-consistent Born approximation. It is found that electron–phonon scattering effect is more pronounced at ON-state of Si NW FET. The ballistic current decreases with the decrease in diameter of the Si NW FET due to electron–phonon scattering.

The aim of this work is to fabricate high-crystalline nanoporous zinc oxide (ZnO) thin films by a modified thermal evaporation system. First, zinc thin films have been deposited on bare glass substrate by the modified thermal evaporation system with pressure of 0.05mbar, source–substrate distance of 3cm and source temperature 700${}^{\circ }$C. Then, high-crystalline ZnO thin film is obtained by annealing at 500${}^{\circ }$C for 2h in atmosphere. The prepared ZnO films are characterized with various deposition times of 10min and 20min. The structural property was investigated by X-ray diffractometer (XRD). The optical bandgap and absorbance/transmittance of these films are examined by ultraviolet/visible spectrophotometer. The surface morphological property has been observed by scanning electron microscope (SEM). ZnO films have showed uniform nanoporous surface with high-crystalline hexagonal wurtzite structure. The ZnO films prepared with 20min has excitation absorption-edge at 369nm, which is blueshifted with respect to the bulk absorption-edge appearing at 380nm. The gap energy of ZnO film is decreased from 3.14eV to 3.09eV with increase of the deposition time, which can enhance the excitation of ZnO films by the near visible light, and is suitable for the application of photocatalyst of waste water cleaning and polluted air purification.

This paper deals with the performance of both gate and drain control coefficients to analyze the behavior of carbon nanotube field effect transistors (CNTFETs) under ballistic conditions and based on the change of different parameter value, such as oxide thickness of structure and temperature variation. A thorough study of both gate and drain control coefficient effects on the performance of CNTFETs has been conducted under different temperature and oxide layers and the output of the device has been analyzed through different parameters. Higher values of control coefficient help to attain larger transconductance by the increasing temperatures. For a fixed value of control coefficient, 4nm thickness of oxide has a transconductance of $\sim$ 4.5 $\times$ 10${}^{-5}$ S/m. Smaller oxide layer thickness has higher slope of increment in transconductance value. ON-state current to leakage current ratio shows a steady state response toward increment of gate control coefficient. Also, increment of oxide thickness has an adverse effect on current ratio, while a linear decay of current ratio is observed with the increased value of drain controlled one. Drain-induced battery lowering (DIBL) effect decreases with the value of gate control one and increases with the drain control coefficient. In this way, the optimum value for both the control coefficients has to be considered in order to perform well.

In this paper, study on the capacitive effects of Graphene nanoribbon (GNR) in VLSI interconnect has been studied as a function of GNR width, Fermi function and gate voltage. The quantum capacitance of GNR has been simulated in terms of Fermi function for three different values of insulator thickness — 1.5nm, 2nm and 2.5nm. After that, quantum capacitance is studied in both degenerate and nondegenerate region with respect to Fermi function and gate voltage of range 1–5V. Then, the total capacitance of GNR is studied as a function of gate voltage of $-2$–5V range at degenerate and nondegenerate regions, where width of GNR is considered 4nm. Finally, the total capacitance of GNR is studied in both regions with varying GNR width, considering fixed gate voltage of 3V. After analyzing these simulations, it has been found that GNR in degenerate region shows nearly steady capacitance under a certain applied gate voltage.