SPIN

Reconfigurable computing provides a number of advantages such as low Research and Development (R&D) cost and design flexibility when compared to application specific logic circuits (ASLC). However its low power efficiency greatly limits its applications. One of the major reasons of this shortcoming is that Static Random Access Memory (SRAM)-based configuration memory occupies a large die area and consumes high static power. The later is more severe due to the rapidly increasing leakage currents, which are intrinsic and become worse following the fabrication node shrinking. Spintronic memories (e.g., STT-MRAM and racetrack memory (RM)) are emerging nonvolatile memory technologies under intense investigation by both academics and industries. They promise ultra-high storage density, nonvolatility and low power. In this paper, we review the current status of spintronic memories for reconfigurable computing, the related device-circuit-system design requirements and present its perspectives. Mixed simulations based on spintronic device compact models show its high density and low power performance when compared to conventional SRAM-based reconfigurable computing.

Narrow gap III–V semiconductors have been investigated for semiconductor spintronics. By alloying these semiconductors with manganese magnetic semiconductors result. Large magnetoresistance (MR) effects have been observed in narrow gap magnetic semiconductor p–n heterojunctions. The MR which is positive is attributed to spin selective carrier scattering. For an InMnAs/InAs heterojunction a diode MR of 2680% is observed at room temperature and high magnetic fields. This work indicates that highly spin-polarized magnetic semiconductor heterojunctions can be realized that operate at room temperature. Devices based on the MR include spin diodes and bipolar magnetic junction transistors. We utilize the diode MR states to create a binary logic family.

High performance computing system design based on complementary metal oxide semiconductor (CMOS) is facing more and more challenges due to the volatility, increased leak current and interconnection delay. Computations utilizing magnetic logic devices have attracted considerable interest as the potential alternatives because of their features of nonvolatility, re-configurability, unlimited endurance and low power consumption. Instead of using electron charges, the magnetic logic device stores and processes the data information by controlling spins, i.e., the magnetization states in a device. The emerging technologies related to the magnetic logic are mainly composed of three design schemes, i.e., the magnetoresistive logic, the magnetic quantum cellular automata and the magnetic domain wall logic. This paper will illustrate the principles as well as review the recent developments of these magnetic logic devices. Challenges and prospects of the future development are also discussed.

The propagation of a kink soliton through a perpendicularly magnetized antiferromagnetically coupled multilayer stack has been imaged by scanning laser Kerr microscopy. The soliton behavior allows layer-by-layer reversal leading to clear evidence of changes of switching behavior of different layers in the stack. We find that the density of domain nucleation sites is dependent on the configuration of the neighboring layers as well as height up the stack. By growing a series of single layer and coupled trilayer samples, we are able to explain the trends in nucleation seen in the soliton stack in terms of pinhole and orange peel coupling, in agreement with STEM (Scanning transmission electron microscope) imaging.

This paper presents an architecture-level approach, called nonvolatile logic-in-memory (NV-LIM) architecture, to solving performance-wall and power-wall problems in the present CMOS-only-based logic-LSI (Large-Scaled Integration) processors. The use of magnetic tunnel junction devices combined with a CMOS-gate style makes it possible to achieve a high-performance and ultra-low-power logic LSI. Some concrete examples using the proposed method allow you to achieve the desired performance improvement compared to a corresponding CMOS-only-based realization.