Oxide Reliability

The following sections are included:

• FOREWORD

• CONTENTS

The subject of oxide wearout, breakdown, and reliability will be reviewed, largely, from an historical perspective. Five topics will be discussed: oxide breakdown, oxide leakage currents, trap generation, statistics, and reliability. An early model of oxide breakdown, developed by Klein and Solomon, will be described and will be shown to be generally applicable to oxide manufactured today, and to other solid insulators, as well. Both hard and soft breakdown were included in this model and will be discussed here. The importance of stress-induced-leakage-currents (SILCs) and direct tunneling currents will be discussed in the context of device applications, thinner oxides, and oxide reliability. The diminishing importance of breakdown in ultra thin oxides in ultra small devices will be contrasted with the increasing importance of oxide leakage currents. Trap generation is important in the triggering of breakdown and in the formation of SILCs. Trap generation will be discussed in some detail. Various statistical formulations of oxide breakdown, and how these distributions are related to trap generation, will be discussed. All of these effects will be related to oxide reliability and oxide integrity. An extensive bibliography has been included to help the reader obtain more detailed information concerning the concepts being discussed.

This paper reviews the reliability of Flash nonvolatile memories, with particular attention to dielectric degradation. These memories are manufactured with the same materials and processing steps as are other types of IC's, but unique features of Flash memories create very different reliability challenges. These features stem from the three unique functions of the Flash cell: to program, to erase, and to retain charge for years. Each of these functions has its own characteristic degradation mechanisms. A fascinating aspect of Flash reliability is the insight that can be gained into dielectric degradation mechanisms. In normal use, Flash dielectrics experience levels of electric field, hot-carrier bombardment, and charge fluence that other IC processes experience only in capacitor breakdown studies and other accelerated stresses. Catastrophic breakdown does not occur, however, because the stress from charging and discharging the floating-gate capacitor is fundamentally self-limiting. At the same time, dielectric leakage of a few electrons a day can be measurable in a Flash cell. The combination of high stress, self-limiting degradation, and high leakage sensitivity allows prebreakdown dielectric degradation to be studied in great detail. Although Flash memory technology poses unique development challenges, engineering optimization can make these memories highly reliable.

A molecular physics-based complementary model, which includes both field-induced and current-induced degradation mechanisms, is used to help resolve the E versus 1/E time-dependent dielectric breakdown (TDDB) model controversy that has existed for many years. The Complementary Model indicates either the E or 1/E–TDDB model can be valid for certain specified field, temperature, and molecular bonding-energy ranges. For bond strengths < 3 eV, the bond breakage rate is generally dominated by field-enhanced thermal processes at lower fields and elevated temperatures where the E-model is valid. At higher fields, lower temperatures and higher bond strengths the bond breakage mechanism must be hole-catalyzed and the TDDB physics is described well by the 1/E-model. Neither the E-model nor 1/E-model works well for oxide thickness below t_ox < 4 nm where direct tunneling effects dominate in these hyper-thin films. The increase in DT leakage leads to more hole injection and trapping in the SiO₂. This enhanced dielectric degradation rate with t_ox reduction can be easily incorporated into the Complementary Model where hole capture serves to catalyze Si–O bond breakage.

The dielectric breakdown of ultra-thin silicon dioxide films used as gate insulator in MOSFETs is one of the most important reliability issues in CMOS technology. In this paper, two main aspects of oxide breakdown are considered: the modeling of the breakdown statistics and the properties of the two main breakdown modes, namely Soft Breakdown and Hard Breakdown. The most invoked models for the breakdown statistics that relate defect generation and breakdown are reviewed. Particular attention is paid to the percolation models and to a recent cell-based analytic picture. The scaling of the breakdown distribution with oxide thickness is considered and it is shown that both pictures are equivalent for ultra-thin oxides. It is shown that soft and hard breakdown show coincident statistics and this is used to conclude that both breakdown modes are triggered by the formation of the same kind of defect-related conduction paths. The big differences in the post-breakdown conduction properties are attributed to phenomena occurring during the very fast breakdown current runaway that determine the area of the final breakdown spot. The properties of soft and hard breakdown are explained within the common framework of a model based on quantum-point-contact conduction. This mesoscopic approach to the post-breakdown conduction is shown to explain the main experimental results including conductance quantization after hard breakdown, the area and thickness independence of the soft-breakdown I(V) characteristics and the statistical correlation between current level and normalized conductance. Finally, we deal with some open questions and relevant issues that are now subject of intensive investigations. The fact that some breakdown events can be tolerated for some digital applications is considered. In this regard, the distinction between breakdown and device failure distributions is made and some implications for device reliability are discussed. It is argued that energy dissipation during the breakdown runaway can determine the breakdown efficiency, the prevalence ratio of soft to hard breakdown, and their variations with stress conditions, experimental setup (series impedance) and sample characteristics.

We review the development of the anode hole injection (AHI) model for reliability projection of the silicon dioxide gate dielectric. The experimental and theoretical foundation of the AHI model is presented. Recent development and implications for the reliability of ultra-thin oxides are discussed. AHI is used to illuminate the questions of E versus 1/E models and field-driven versus voltage-driven models. Building on the concept of effective thinning, the AHI model is applied for the interpretation of defect-induced breakdown data and for optimizing oxide screening conditions. Circuit level reliability projection as a function of operating time, temperature, and power supply voltage is also illustrated.