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A CMOS Low-Power Digital Variable Gain Amplifier Design for a Cognitive Radio Receiver “Application for IEEE 802.22 Standard”

Laboratory of Electronics and Technologies of Information (LETI), University of Sfax, ENIS, B. P. 1173-3038, Sfax, Tunisia

E-mail Address: sawssenlahiani@yahoo.fr

Corresponding author.

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Samir Ben Salem

Laboratory of Electronics and Technologies of Information (LETI), University of Sfax, ENIS, B. P. 1173-3038, Sfax, Tunisia

E-mail Address: benselem.samir@gmail.com

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Houda Daoud

Laboratory of Electronics and Technologies of Information (LETI), University of Sfax, ENIS, B. P. 1173-3038, Sfax, Tunisia

E-mail Address: dhleti@yahoo.fr

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, and

Mourad Loulou

Laboratory of Electronics and Technologies of Information (LETI), University of Sfax, ENIS, B. P. 1173-3038, Sfax, Tunisia

E-mail Address: mourad.loulou@ieee.org

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https://doi.org/10.1142/S0218126618501359Cited by:3 (Source: Crossref)

Abstract

This paper presents the design of a new Digital Variable Gain Amplifier cell (DVGA). The proposed circuit based on transconductance, gm, amplifier and a transconductance amplifier is analyzed and designed for a cognitive radio receiver. The variable-gain amplifier (VGA) proposed consists of a digital control block, an auxiliary pair to retain a constant current density, and offers a gain-independent bandwidth (BW). A novel cell structure is designed for high gain, high BW, low power consumption and low Noise Figure (NF). The Heuristic Method is used to optimize the proposed circuit performance for high gain, low noise and low power consumption. This circuit is implemented and simulated using device-level description of TSMC 0.18 $μ$ $μ$ m CMOS process. Simulation results show that the DVGA can provide a gain variation range of 54dB (from 54dB to 0dB) with a 3dB BW over more than 110MHz. The circuit consumes the maximum power of 0.65mW from a 1.8V supply.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

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