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Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

In this paper, a wideband receiver front-end including the flexible reconfigurable main and auxiliary paths is proposed. Therein, the main path has the low-noise advantage thanks to the low-noise transconductance amplifier (LNTA) preceding the mixer and baseband. Meanwhile, by utilizing a mixer-first structure, the auxiliary path renders a high in-band and out-of-band linearity. Furthermore, an inductor resonance structure is also designed to mitigate the baseband noise crosstalk issue which is disclosed by a charging/discharging mechanism via the tail capacitance of passive mixers. Both of the receiving paths have shared a common baseband circuit while loading a commonly-shared 25% duty-cycle LO source generator. Simulation results by a 180 nm CMOS have demonstrated that the main path provides a low noise figure (NF) of 2.7 dB, while the auxiliary path obtains the in-band and out-of-band IIP3 of 9.2 and 21 dBm under typical LO excitation frequency of $f_{\mathrm{\text{LO}}}=1.25$ GHz. The power consumption of the main path of the dual-path front-end is 57 mW and that of the auxiliary path is 26 mW under a supply voltage of 1.8 V.

This paper presents the design of a new Digital Variable Gain Amplifier cell (DVGA). The proposed circuit based on transconductance, gm, amplifier and a transconductance amplifier is analyzed and designed for a cognitive radio receiver. The variable-gain amplifier (VGA) proposed consists of a digital control block, an auxiliary pair to retain a constant current density, and offers a gain-independent bandwidth (BW). A novel cell structure is designed for high gain, high BW, low power consumption and low Noise Figure (NF). The Heuristic Method is used to optimize the proposed circuit performance for high gain, low noise and low power consumption. This circuit is implemented and simulated using device-level description of TSMC 0.18$\mu$m CMOS process. Simulation results show that the DVGA can provide a gain variation range of 54dB (from 54dB to 0dB) with a 3dB BW over more than 110MHz. The circuit consumes the maximum power of 0.65mW from a 1.8V supply.

Operational Transconductance Amplifier (OTA) is an important circuit block used in the design of filter, amplifiers and oscillators for various analog-mixed circuit systems. However, design of a low-noise, high-gain OTA with low-power consumption is a challenging task in CMOS technology owing to high-power requirements of OTA for emulating high gain. This paper represents the design of gate-driven quasi-floating bulk recycling folded cascode (GDQFB RFC) OTA which has been shown to provide low-noise operation, emulates high gain and draws very less power. The design utilizes the gate-driven quasi-floating bulk (GDQFB) technique on a recycling folded cascode structure, which enhances the transconductance of OTA and improves its performance. All the post-layout simulation results have been obtained in 0.18-μm CMOS N-well technology using BSIM3V3 device models. The obtained results indicate very high gain of 100.4 dB, gain-bandwidth of 69 kHz, phase margin of 51.9^∘ with power consumption of 2.31μW from ±0.9V supply voltage. The input referred noise emulated by proposed OTA is 0.684, 0.21 and 0.0592μV/√Hz @ 1 Hz, 10 Hz and 1 kHz, respectively. The input common mode range and output voltage swing are found to be −0.402 to 0.669 V and −0.493 to 0.610 V, respectively. Corner simulations and Monte Carlo analysis have been performed to verify the robustness of the proposed OTA. The proposed OTA can be used in design of filters and amplifiers for bio-instruments, sensor applications, neural recording applications and human implants etc.

This paper presents the design of an efficient operational transconductance amplifier (OTA) to be explicitly used for electroencephalogram (EEG) signal acquisition in neural amplifiers (NAs). The central objective of this study revolves around addressing the fundamental compromise between noise and power in the design of NAs. The overarching goal is to effectively mitigate this trade-off by introducing novel approaches. The proposed design’s novelty lies in utilizing an adaptive biasing technique instead of the traditional current mirror biasing technique. Furthermore, the conventional input differential pair of the OTA is modified to employ a self cascode flipped voltage follower (SCFVF), which eventually reduces power consumption of the NA to 0.822 $\mu$W. Additionally, notable improvements in noise performance are achieved and found to be 624.9 nV/$\sqrt{(}Hz)$ at 1 Hz. The gain and bandwidth range of the input low-noise amplifier is 54.2 dB and 2.8 Hz–207 Hz, respectively, which effectively amplifies low-amplitude noisy incoming signals, addressing the specific requirements of EEG signal acquisition.