Journal of Circuits, Systems and Computers

This review paper describes different lumped circuitry realizations of the chaotic dynamical systems having equilibrium degeneration into a plane object with topological dimension of the equilibrium structure equals one. This property has limited amount (but still increasing, especially recently) of third-order autonomous deterministic dynamical systems. Mathematical models are generalized into classes to design analog networks as universal as possible, capable of modeling the rich scale of associated dynamics including the so-called chaos. Reference state trajectories for the chaotic attractors are generated via numerical analysis. Since used active devices can be precisely approximated by using third-level frequency dependent model, it is believed that computer simulations are close enough to capture real behavior. These simulations are included to demonstrate the existence of chaotic motion.

In today’s embedded technology, memories are the universal components. With the onset of the deep-submicron VLSI technology, the density and capacity of the memory are growing. However, providing a cost-effective test solution for these on-chip memories is becoming a challenging task. As memory and other processing cores have been embedded deeply in system chips, the IEEE std 1500 has been suggested to facilitate the test of these core types. Whereas up to now this standard has not presented a definite solution for testing of memory cores, in this paper, we proposed a programmable IEEE 1500-compliant wrapper for applying several Mach algorithms on word-oriented memory cores to reach the desired fault coverage. The proposed wrapper is without finite-state-machine controller, and as a result, the complexity of wrapper circuitry is low and hardware redundancy is acceptable as well.

This paper presents the design of a new Digital Variable Gain Amplifier cell (DVGA). The proposed circuit based on transconductance, gm, amplifier and a transconductance amplifier is analyzed and designed for a cognitive radio receiver. The variable-gain amplifier (VGA) proposed consists of a digital control block, an auxiliary pair to retain a constant current density, and offers a gain-independent bandwidth (BW). A novel cell structure is designed for high gain, high BW, low power consumption and low Noise Figure (NF). The Heuristic Method is used to optimize the proposed circuit performance for high gain, low noise and low power consumption. This circuit is implemented and simulated using device-level description of TSMC 0.18$\mu$m CMOS process. Simulation results show that the DVGA can provide a gain variation range of 54dB (from 54dB to 0dB) with a 3dB BW over more than 110MHz. The circuit consumes the maximum power of 0.65mW from a 1.8V supply.

In this study, electronically-tunable, current-mode, square-root-domain, third-order low-pass filter is proposed. The study is carried out with three circuit designs. First circuit is third-order low-pass Butterworth filter, second circuit is third-order low-pass Chebyshev filter and the last circuit is third-order low-pass elliptic filter. All the input and output values of the filter circuit are current. Only grounded capacitors and MOSFETs are required in order to realize the filter circuit. Additionally, natural frequency $f_0$ of the current-mode filter can be adjusted electronically using outer current sources. To validate the theory and to demonstrate the performance of third-order filter, frequency and time domain simulations of PSPICE program are used. To that end, TSMC 0.35$\mu$m Level 3 CMOS process parameters are utilized to realize the simulations of the filter.

This paper presents a supper class-AB adaptive biasing bulk-driven amplifier for ultra-low-power applications. In the proposed structure, two bulk-driven flipped voltage follower (FVF) cells are reconfigured as nonlinear tail currents using quasi-floating gate method to enhance transconductance and slew rate. In addition, two idle current controllers are employed as common source amplifiers to provide a supper class-AB structure without increasing total current consumption. The proposed structure is simulated in 0.18-$\mu$m CMOS technology at 0.5V supply with 35nW power budget. The results show a 57.9dB DC gain, 8.8kHz gain bandwidth and 38.2V/ms slew rate for the proposed amplifier.

Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps. The HTHs are very small and can cause damages in circuit function. They cannot be detected by conventional testing methods. Due to dangerous effects of them, Hardware Trojan Detection has become a major concern in hardware security. In this paper, a new HTH detection method is presented based on side-channel analysis that uses path delay measurement. In this method, we find and observe the paths that Trojans have most effect on them. Most of the previous works add some structures to the circuit and need a large overhead cost. But, in our method, there is no modification in the circuit and we can use it for testing the circuits received after fabrication. The proposed method is evaluated with Xilinx FPGA over a number of test circuits. The results show that measuring the delays on 20 paths with an accuracy of 0.01ns can detect more than 80% of Trojans.

Impulse noise is an image noise that degrades the quality of the image drastically. In this paper, k-means clustering has been incorporated with fuzzy-support vector machine (FSVM) classifier for classification of noisy and non-noisy pixels in removal of impulse noise from gray images. Here, local binary pattern (LBP) has been incorporated with previously used feature vector prediction error of the processing pixel, absolute difference between median value and processing pixel, median pixel, pixel under operation and mean value around the processing kernel. In this work, $k$-means clustering has been used for reducing the feature vector set, where features have been extracted from the images corrupted with 10%, 50%, and 90% impulse noise. If the pixel is depicted as noisy in testing phase, histogram adaptive fuzzy filter is processed over the noisy pixel under operation. It is seen that the proposed filter offers improved performance over some of the state-of-the-art filter in terms of different image quality measures likely PSNR, SSIM, MSE, FSIM, etc. It is observed that performance is increased by $\sim$2–5dB than baseline filters likely SVM fuzzy filter, and artificial neural network based adaptive sized mean filter (ANNASMF) especially at high density noise.

One of the main challenges in signal denoising is to accurately restore useful signals in low signal-to-noise ratio (SNR) scenarios. In this paper, we investigate the signal denoising problem for multi-component linear frequency modulated (LFM) signals. An effective time-frequency (TF) analysis-based approach is proposed. Compared to the existing approaches, our proposed one can further increase the noise suppressing performance and improve the quality of the reconstructed signal. Experimental results are presented to show that the proposed denoising approach is able to effectively separate the multi-component LFM signal from the strong noise environments.

A low voltage analog VLSI circuit model for Hodgkin–Huxley (HH) neuron cell equations (HH neuron model) is presented. Floating gate MOSFET (FGMOS) transistors in weak inversion region have been used to model HH equations such as gating variables, $\alpha$ and $\beta$ functions and combined action of $m$, $n$ and $h$. The combination of $m$, $n$ and $h$ controls the Na$+$ and K$+$ channel currents. The superiorities of the proposed circuits are low supply voltage, low power consumption, less circuit complexity and as a result, low costs are compared to the previous works. The proposed circuit which uses 24 transistors is simulated in Hspice software using 0.18$\mu$ technology and consumes 119$\mu$W.

A two-dimensional digital-to-analog converter (DAC) structure compatible with dynamic element matching (DEM) methods is presented. Unlike the DACs using segmented structure for employing DEM, the new structure randomizes inter-segment error. This advantage is achieved because of the characteristics of the algorithm of two-dimensional decoding. The simulation results in 180nm CMOS technology, 319.72MHz signal frequency and 800MS/s sample rate for an 8-bit two-dimensional DAC utilizing the presented structure, shows 14.94dB spurious-free dynamic range (SFDR) improvement compared to the SFDR of the same DAC without employing the presented structure. Also, the IMD3 of the DAC employing the presented structure for $F_{\mathrm{\text{in1}}}=317.77$MHz and $F_{\mathrm{\text{in2}}}=319.72$MHz is 50.1dB.

This paper presents a $2\times V_{DD}$-enabled output-capacitor-free CMOS low-dropout (LDO) regulator with fast transient response for cost-effective system-on-chip (SoC) power management applications with elevated-$V_{DD}$ supply. All the MOS transistors used in the proposed LDO regulator are low voltage (LV) MOSFETs, hence saving the high voltage devices fabrication cost required in a conventional design. Two LV power transistors are cascaded in the power train. A mid-rail regulator is used to generate $1\times V_{DD}$ voltage for the power transistors as well as the main error amplifier to guarantee safe operation. The mid-rail regulator employs stacking transistors to handle the high supply voltage. Moreover, Miller compensation with adaptive biasing is used to achieve good stability and fast transient response. A proof-of-concept design is fabricated in a standard 0.18-$\mu$m CMOS process which achieves 3.3–3.6V nominal input, 3.1V nominal output and 100mA loading capability with all the transistors being 1.8V MOSFETs.

Decreasing the scale of transistors and exponential increase in the transistor counts has made the soft-errors as one of the major causes of software failures. Fault injection is a powerful method for dependability assessment of a computer system against soft-errors. A considerable number of randomly injected faults in the current methods and tools are effect-less or equivalent. To overcome this problem and reduce the cost of fault injection, this study presents a software based fault-injection method that accurately evaluates the dependability of a computer system with a limited number fault-injection. Using a genetic algorithm (GA) the most vulnerable executable paths of an input program is identified; then only the basic blocs (BBs) into the identified vulnerable paths are considered as the target of fault injection. The results of fault injections on the set of 8 traditional benchmark-programs show that the proposed method reduces about 20% of effect-less faults by avoiding the injection of faults in the error-derating blocks of a program. Furthermore, the number of injected faults is reduced to 60% of its original size in the random injection. Also, the proposed method provides more stable and accurate results than the random injection.

This paper concerns the design space exploration (DSE) of Reconfigurable Multi- Processor System-on- Chip (MPSoC) architectures. Reconfiguration allows users to allocate optimum system resources for a specific application in such a way to improve the energy and throughput balance. To achieve the best balance between power consumption and throughput performance for a particular application domain, typical design space parameters for a multi-processor architecture comprise the cache size, the number of processor cores and the operating frequency. The exploration of the design space has always been an offline technique, consuming a large amount of time. Hence, the exploration has been unsuitable for reconfigurable architectures, which require an early runtime decision. This paper presents Approximate Computing DSE (AC-DSE), an online technique for the DSE of MPSoCs by means of approximate computing. In AC-DSE, design space solutions are first obtained from a set of optimization algorithms, which in turn are used to train a neural network (NN). From then on, the NN can be used to rapidly return its own solutions in the form of design space parameters for a desired energy and throughput performance, without any further training.

As the performing ability of a silicon chip relies on the power supply voltage, it must be configured using genuine power and ground bond pads for mitigating power and ground noise (PGN), which is directly boosted by the increasing peaks of instantaneous current $i(t)$ and current ramp $(di/dt)$. To address the same, a novel and compact clock gating (CG) scheme is unveiled in this paper to effectively control the peak of $i(t)$ and $di/dt$, thereby subduing PGN. The new CG arrangement is simulated for 90nm Predictive Technology Model (PTM90), where it is observed that the scheme reduces 88.80% of $i(t)$ and 84.19% of average $di/dt$ in comparison to its no gating counterpart along with a reduction of 80.14% in average power dissipation. These results are found to be more prominent when the proposed circuit configuration is tested in 90nm Generic Process Design Kit (GPDK90), proclaiming 88.75% and 84.34% reduction in average $di/dt$ and average power, respectively, to illustrate its capability of truncating PGN in silicon chips.

This paper propounded a novel method of design and realization of a digital fuzzy controlled buck integrated power factor correction (PFC) converter. It derives its advantages through the low buck capacitor voltage and single control switch (SW1), which leads to reduced complex control and price. Sub-harmonic oscillations generated in the peak current mode technique can be nullified by using the ramp signal, thereby improving the overall performance of the converter. The fuzzy logic controller (FLC) is robust and effective than the conventional linear controllers like P, PI, PID. In this paper, the digital fuzzy current mode controlled integrated PFC converter with external ramp compensation signal for 100 W load operating in the universal range of voltage (90V–265V), 50Hz has been designed and implemented using MATLAB/Simulink, verified in hardware using the TMS320F2812 digital processor board, and the results are found to be complying with international regulatory standards (IEC 6100-3-2 and IEEE 519-1992).

As the key component of wireless network-on-chip (WiNoC), wireless router is required to handle a large number of data packets which could cause network congestion. The congestion not only reduces the network performance, but also results in additional power consumption. In this paper, a low-power WiNoC with congestion-aware wireless node is proposed. Firstly, flit counter unit and address resolution unit are added in wireless interface (WI), which can sense the congestion information and destination address information of each wireless node dynamically. Secondly, through the proposed congestion judgment algorithm, the congestion judgment unit in global network can judge the priority of each wireless node pair and set the highest-priority wireless node pair to use the channel resources preferentially. The mechanism can effectively alleviate the congestion of wireless nodes and ensure the stability of system performance. In addition, a sleep mechanism is utilized to switch off WI which fails in the wireless channel competition. Experimental results show that the proposed scheme can effectively improve the performance in terms of packets’ transmission latency and network throughput.

This paper considers the noise modeling of interconnections in on-chip communication. We present an approach to illustrate modeling and simulation of interconnections on chip microsystems that consist of electrical circuits connected to subsystems described by partial differential equations, which are solved independently. A model for energy dissipation in RLC mode is proposed for the switching current/voltage of such on-chip interconnections.

The Waveform Relaxation (WR) algorithm is presented in this paper to address limiting in simulating NoCs due to the large number of coupled lines.

We describe our approach to the modeling of on-chip interconnections. We present an applicative example of our approach with VHDL-AMS implementations and simulation results. This article analyzes the coupling noise, the bit error rate (BER) as well as the noise as a function of the rise/fall time of the signal source which can significantly limit the scalability of the NoCs.