Research PapersNo Access

A Program-Aware Fault-Injection Method for Dependability Evaluation Against Soft-Error Using Genetic Algorithm

Bahman Arasteh

Department of Computer Engineering, Tabriz Branch, Islamic Azad University, Tabriz, Iran

https://doi.org/10.1142/S021812661850144XCited by:1 (Source: Crossref)

Abstract

Decreasing the scale of transistors and exponential increase in the transistor counts has made the soft-errors as one of the major causes of software failures. Fault injection is a powerful method for dependability assessment of a computer system against soft-errors. A considerable number of randomly injected faults in the current methods and tools are effect-less or equivalent. To overcome this problem and reduce the cost of fault injection, this study presents a software based fault-injection method that accurately evaluates the dependability of a computer system with a limited number fault-injection. Using a genetic algorithm (GA) the most vulnerable executable paths of an input program is identified; then only the basic blocs (BBs) into the identified vulnerable paths are considered as the target of fault injection. The results of fault injections on the set of 8 traditional benchmark-programs show that the proposed method reduces about 20% of effect-less faults by avoiding the injection of faults in the error-derating blocks of a program. Furthermore, the number of injected faults is reduced to 60% of its original size in the random injection. Also, the proposed method provides more stable and accurate results than the random injection.

This paper was recommended by Regional Editor Tongquan Wei.

Keywords:

References

1. S. Bahramnejhad and H. R. Zarandi. Mitigation of soft errors in SRAM-based FPGAs using CAD tools, Comput. Electr. Eng. 37 (2011) 1019–1031. Crossref, Web of Science, Google Scholar
2. P. Shivakumar, M. Kistler, S. Keckler, D. Burger and L. Alvisi, Modeling the effect of technology trends on soft error rate of combinational logic, Proc. Int. Conf. Dependable Systems and Networks (DSN), June 2002. Google Scholar
3. T. J. Slegel, R. M. Averill, M. A. Check, B. C. Giamei, B. W. Krumm, C. A. Krygowski, W. H. Li, J. S. Liptay, J. D. MacDougall, T. J. McPherson, J. A. Navarro, E. M. Schwarz, K. Shum and C. F. Webb, IBM’s S/390 G5 Microprocessor Design, IEEE Micro. 19 (1999) 12–23. Crossref, Web of Science, Google Scholar
4. N. Oh, S. Mitra and E. J. McCluskey, ED⁴ I: Error detection by diverse data and duplicated instructions, IEEE Trans. Comput. 51 (2002) 180–199. Crossref, Web of Science, Google Scholar
5. T. Tsai et al., Stress-based and path-based fault injection, IEEE Trans. Comput. 48 (1999) 1183–1201. Crossref, Web of Science, Google Scholar
6. T. Austin, E. Larson and D. Ernst, SimpleScalar: An Infrastructure for computer system modeling, IEEE Comput. 35 (2002) 59–67. Crossref, Web of Science, Google Scholar
7. K. Pattabiraman, G. P. Saggese, D. Chen, Z. Kalbarczyk and R. Iyer, Dynamic derivation of application-specific error detectors and their implementation in hardware, Proc. 6th Int. Conf. Dependable Computing (2006). Google Scholar
8. S. J. Chen, P. A. Hesuing and Y. H. Hu, Hardware Software Codesign of Multimedia SOC Platform (Springer Science & Business Media, ISBN: 978-1-4020-9622-8, 2009). Google Scholar
9. M. Li, P. Ramachandran, S. Sahoo, S. Adve, V. Adve and Y. Zhou, SWAT: An error resilient system, Proc. Fourth Workshop on Silicon Errors in Logic-System Effects, SELSE-IV (2008). Google Scholar
10. L. Aiguo and H. Bingrong, On-line control flow error detection using relationship signatures among basic blocks, Comput. Electr. Eng. 36 (2010) 132–141. Crossref, Web of Science, Google Scholar
11. S. Benso, P. Chiusano, L. Prinetto and Tagliaferri, C/C $+ +$ source-to-source compiler for dependable applications, Proc. IEEE Int. Conf. Dependable Systems and Networks (DSN), June 2000. Google Scholar
12. V. Sridharan, D. R. Kaeli, Using PVF traces to accelerate AVF modeling, Proc. IEEE Workshop on Silicon Errors in Logic — System Effects, Stanford, California, March 2010. Google Scholar
13. A. Savino, S. D. Carlo, G. Politano, A. Benso and G. Dnatale, Statistical reliability estimation of microprocessor-based systems, IEEE Trans. Comput. 61 (2012) 1521–1534. Crossref, Web of Science, Google Scholar
14. A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto and L. Tagliaferri, Data Criticality Estimation in Software Application, Proc. International Test Conf., October 2003, pp. 802–810. Google Scholar
15. M. Rebaudengo, M. Sonza Reorda, M. Torchiano and M. Iolante, A source-to-source compiler for generating dependable software, Proc. IEEE Int. Workshop on Source Code Analysis and Manipulation, November 2001, pp. 33–42. Google Scholar
16. D. Borodin, B. H. H. Juurlink, Protective redundancy overhead reduction using instruction vulnerability factor, Proc. ACM Int. Conf.Computing Frontiers, Italy, May 2010, pp. 319–326. Google Scholar
17. N. Seifert, Xiaowei Zhu and L. W. Massengill, Impact of scaling on soft-error rates in commercial microprocessors, IEEE Trans. Nucl. Sci. 49 (2002) 3100–3106. Crossref, Web of Science, Google Scholar
18. G. A. Reis, J. Chang, N. Vachharajani, R. Rangan and D. I. August, SWIFT: Software implemented fault tolerance, Proc. Int. Symp. Code Generation and Optimization (CGO’05), 2005. Google Scholar
19. J. Karlsson, Reliability Evaluation of a Fault-Tolerant Computer for a Multi-phased Mission and a Use of Heavy-ion Radiation for Fault Injection Experiments, PhD Thesis, School of Electrical and Computer Engineering, Chalmers University of Technology, 1990. Google Scholar
20. M. Evers, Improving Brnach Prediction by Understanding Branch Behaviour, Phd. Thesis, University of Michgan, 2000. Google Scholar
21. X. Li, Exploiting Inherent Program Redundancy for Fault Tolerance, PHD Thesis in University of Maryland, 2009. Google Scholar
22. F. Shuguang, G. Shantanu, A. Ansari and S. Mahlke, Shoestring: Probabilistic soft-error resilience on the cheap, Proc. 15th Int. Conf. Architectural Support for Programming Languages and Operating Systems, March 2010. Google Scholar
23. D. Thaker, D. Franklin, J. Oliver, S. Biswas, D. Lockhart, T. Metodi and F. T. Chong, Characterization of error-tolerant applications when protecting control data, Proc. IEEE Int. Symp. Workload Characterization, October 2006. Google Scholar
24. H. Madeira and J. Silva, Experimental evaluation of the fail-silent behavior in computers without error masking, Proc. FTCS-24, June 1994, pp. 350–359. Google Scholar
25. P. Yuste et al., Non-Intrusive software-implemented fault injection in embedded systems, LADC 2003, LNCS 2847, 2003, pp. 23–38. Google Scholar
26. B. Arasteh, Improving the resiliency of software against soft-errors without external redundancy and performance overhead, J. CIRCUIT SYST COMP, 26 (2017) 1750124–1750158. Link, Web of Science, Google Scholar
27. N. Wang, M. Fertig and S. Patel, Y-branches: When you come to a fork in the road, take it, Proc. Int. Conf. Parallel Architectures and Compilation Techniques, 2003. Google Scholar
28. A. Benso et al., Fault-list collapsing for fault injection experiments, Proc. RAMS 98, January 1998, pp. 383–388. Google Scholar
29. G. P. Saggese, N. J. Wang, Z. T. Kalbarczyk, S. J. Patel and R. K. Iyer, An experimental study of soft errors in microprocessors, IEEE Micro 25 (2005) 30–39. Crossref, Web of Science, Google Scholar
30. M. Weiser, Program slicing, Proc. 5th Int. Conf. Software Engineering (ICSE), 1981. Google Scholar
31. E. Rotenberg, Exploiting Large Ineffectual Instruction Sequences, Technical report, North Carolina State University, November 1999. Google Scholar
32. T. Karnik, P. Hazucha and J. Patel, Characterization of soft errors caused by single event upsets in CMOS process, IEEE Trans. Dependable Secure Comput. 1 (2004) 128–143. Crossref, Web of Science, Google Scholar
33. B. Arasteh, S. G. Miremadi and A. M. Rahmani, Developing inherently resilient software against soft-errors based on algorithm level inherent features, J. Electron. Testing 30 (2012) 193–212. Crossref, Web of Science, Google Scholar
34. M. Zhang and N. Shanbhag, A soft error rate analysis methodology, Proc. IEEE/ACM Int. Conf. Computer-Aided Design, November 2004. Google Scholar
35. J. J. Cook and C. Zilles, A characterization of instruction-level error derating and its implications for error detection, Proc. IEEE Int. Conf. Dependable Systems and Networks (DSN), June 2008. Google Scholar
36. S. K. S. Hari, Low-cost program level detectors for reducing silent data corruptions, Proc. IEEE Int. Conf. Dependable Systems and Networks (DSN), June 2012. Google Scholar
37. R. Chillarege and N. Bowen, Understanding large system failures — A fault injection experiment, Proc. FTCS-19, June 1989, pp. 356–363. Google Scholar
38. J. Güthoff and V. Sieh, Combining software-implemented and simulation-based fault injection into a single fault injection method, Proc. FTCS-25, June 1995, pp. 196–206. Google Scholar
39. D. Binkley, An empirical study of static program slice size, ACM Trans. Softw. Eng. Methodol. 16 (2007) 1–32. Crossref, Web of Science, Google Scholar
40. E. David, Genetic Algorithms in Search, Optimization, and Machine Learning (Addison-Wesley Professional, 1989), ISBN: 0–201-15767-5. Google Scholar
41. B. Boehm and V. R. Basili, Software defect reduction top 10 list, IEEE Comput. 34 (2001) 135–137. Crossref, Web of Science, Google Scholar
42. G. P. Saggese, A. Vetteth, Z. Kalbarczyk and R. Iyer, Microprocessor sensitivity to failures: Control vs. execution and combinational vs. sequential logic, Proc. Int. Conf. Dependable Systems and Networks (DSN), pp. 760–769, July 2005. Google Scholar
43. A. Nair, L. K. John, L. Eeckhout and A. V. F. Stressmark, Towards an automated methodology for bounding the worst-case vulnerability to soft-errors, Proc. 43rd Annual IEEE/ACM Int. Symp. Microarchitecture (MICRO), pp. 125–136, December 2010. Google Scholar
44. P. Ammann and G. Mason, Introduction to Software Testing (Cambridge University Press, New York, 2008). Crossref, Google Scholar
45. D. Lee and J. Na, A novel simulation fault injection method for dependability analysis, IEEE Des. Test Comput. 26 (2009) 0–61. Crossref, Google Scholar
46. A. Lanzaro, On The Quality Of Fault Injection For Off-The-Shelf Components in Safety-Critical Systems, Phd Thesis in NAPOLI University, Italy, 2014. Google Scholar
47. J. Zhou et al., Fault-tolerant task scheduling for mixed-criticality real-time systems, J. Circuit Syst. Comput. 26 (2017) 1750016–1750033. Link, Web of Science, Google Scholar
48. J. Zhou, X. Sharon Hu, Y. Ma and T. Wei, Balancing lifetime and soft-error reliability to improve system availability, Proc. 21st Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 685–690, 2016. Google Scholar