Research PapersNo Access

A 2 $\times$ $\times$ V_DD-Enabled Output-Capacitor-Free Low-Dropout Regulator with Fast Transient Response for Low-Cost System-on-Chip

Department of Electrical and Electronic Engineering, Southern University of Science and Technolgy, Nanshan District, Shenzhen, Guangdong 518055, P. R. China

E-mail Address: zhaosx@mail.sustc.edu.cn

Search for more papers by this author

Chenchang Zhan

Department of Electrical and Electronic Engineering, Southern University of Science and Technolgy, Nanshan District, Shenzhen, Guangdong 518055, P. R. China

E-mail Address: zhancc@sustc.edu.cn

Corresponding author.

Search for more papers by this author

, and

Guigang Cai

Department of Electrical and Electronic Engineering, Southern University of Science and Technolgy, Nanshan District, Shenzhen, Guangdong 518055, P. R. China

E-mail Address: caigg@mail.sustc.edu.cn

Search for more papers by this author

https://doi.org/10.1142/S0218126618501438Cited by:0 (Source: Crossref)

Abstract

This paper presents a $2 \times V_{D D}$ $2 \times V_{D D}$ -enabled output-capacitor-free CMOS low-dropout (LDO) regulator with fast transient response for cost-effective system-on-chip (SoC) power management applications with elevated- $V_{D D}$ $V_{D D}$ supply. All the MOS transistors used in the proposed LDO regulator are low voltage (LV) MOSFETs, hence saving the high voltage devices fabrication cost required in a conventional design. Two LV power transistors are cascaded in the power train. A mid-rail regulator is used to generate $1 \times V_{D D}$ $1 \times V_{D D}$ voltage for the power transistors as well as the main error amplifier to guarantee safe operation. The mid-rail regulator employs stacking transistors to handle the high supply voltage. Moreover, Miller compensation with adaptive biasing is used to achieve good stability and fast transient response. A proof-of-concept design is fabricated in a standard 0.18- $μ$ $μ$ m CMOS process which achieves 3.3–3.6V nominal input, 3.1V nominal output and 100mA loading capability with all the transistors being 1.8V MOSFETs.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

References

1. R. J. Milliken, J. Silva-Martinez and E. Sanchez-Sinencio, Full on-chip CMOS low-dropout voltage regulator, IEEE Trans. Circuits Syst. I, Regul. Pap. 54 (2007) 1879–1890. Google Scholar
2. P. Y. Or and K. N. Leung, An output-capacitorless low-dropout regulator with direct voltage-spike detection, IEEE J. Solid-State Circuits 45 (2010) 458–466. Crossref, Web of Science, Google Scholar
3. C. Zhan and W. H. Ki, An output-capacitor-free adaptively biased low-dropout regulator with subthreshold undershoot-reduction for SoC, IEEE Trans. Circuits Syst. I, Regul. Pap. 59 (2012) 1119–1131. Google Scholar
4. C. J. Park, M. Onabajo and J. Silva-Martinez, External capacitor-less low drop-out regulator with 25 dB superior power supply rejection in the 0.4–4 MHz range, IEEE J. Solid-State Circuits 49 (2014) 486–501. Crossref, Web of Science, Google Scholar
5. M. Saint-Laurent, P. Bassett, K. Lin, B. Mohammad, Y. Wang, X. Chen, M. Alradaideh, T. Wernimont, K. Ayyar, D. Bui, D. Galbi, A. Lester, M. Pedrali-Noy and W. Anderson, A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications, IEEE J. Solid-State Circuits 50 (2015) 81–91. Crossref, Web of Science, Google Scholar
6. Y. Lu, C. Li, Y. Zhu, M. Huang, U. Seng-Pan and R. P. Martins, A 312 ps response-time LDO with enhanced super source follower in 28nm CMOS, IET Electron. Lett. 52 (2016) 1368–1370. Crossref, Web of Science, Google Scholar
7. V. Gupta and G. A. Rincon-Mora, A 5mA 0.6 CMOS Miller compensated LDO regulator with 27dB worst-case power-supply rejection using 60 pF of on-chip capacitance, IEEE Int. Solid-State Circuits Conf. (2007) 520–521. Google Scholar
8. C. Zhan and W. H. Ki, Analysis and design of output-capacitor-free low-dropout regulators with low quiescent current and high power supply rejection, IEEE Trans. Circuits Syst. I, Regul. Pap. 61 (2014) 625–636. Google Scholar
9. P. Hazucha et al., High voltage tolerant linear regulator with fast digital control for biasing of integrated DC-DC converters, IEEE J. Solid-State Circuits 42 (2007) 66–73. Crossref, Web of Science, Google Scholar
10. P.-I. Mak and R. P. Martins, High-/mixed-voltage RF and analog CMOS circuits come of age, IEEE Circuits Syst. Mag. 10 (2010) 27–39. Google Scholar
11. P.-I. Mak and R. P. Martins, A $2 \times V_{D D}$ $2 \times V_{D D}$ -enabled mobile-TV RF front-end with TV-GSM interoperability in 1-V 90-nm CMOS, IEEE Trans. Microw. Theory Tech. 58 (2010) 1664–1676. Crossref, Web of Science, Google Scholar
12. S. M. Saadat, C. Shi and C. Zhan, Charge-recycling circuits including switching power stages with floating rails, US patent 9276562 B2 (2016). Google Scholar
13. Y. H. Lam, W. H. Ki and C. Y. Tsui, Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback, IEEE Asia South Pacific Conf. Design Automation (2006), pp. 104–105. Google Scholar
14. C. Zhan and W. H. Ki, Output-capacitor-free adaptively biased low-dropout regulator for system-on-chips, IEEE Trans. Circuits Syst. I, Regul Pap. 57 (2010) 1017–1028. Google Scholar
15. A. Maity and A. Patra, A single-stage low-dropout regulator with a wide dynamic range for generic applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24 (2016) 2117–2127. Web of Science, Google Scholar
16. J. Zarate-Roldan, M. Wang, J. Torres and E. Sánchez-Sinencio, A capacitor-less LDO with high-frequency PSR suitable for a wide range of on-chip capacitive loads, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24 (2016) 2970–2982. Crossref, Web of Science, Google Scholar