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A low input step-up DC/DC converter and power manager in 0.18-μm CMOS process is presented. The proposed converter can work with the input voltage as low as 20 mV. The extremely low input voltage makes it suitable for energy harvesting and power management. Four logic controlled outputs provide the best voltage for various applications to accommodate low power design requirements. A low current low dropout regulator (LDO) is utilized to provide a regulated 2.2 V output for powering low power processors or other low power integrated circuit (ICs). Reserve energy on the storage capacitor CSTORE provides power when the input voltage source is unavailable, thus prolongs the life of the system and expands the application range. Extremely low quiescent current (6 μA) and high efficiency design (64%@300 μA load current) ensure the fastest possible charge times of the output reservoir capacitor. This work provides a complete power management solution for wireless sensing and data acquisition.

This paper presents a $2\times V_{DD}$-enabled output-capacitor-free CMOS low-dropout (LDO) regulator with fast transient response for cost-effective system-on-chip (SoC) power management applications with elevated-$V_{DD}$ supply. All the MOS transistors used in the proposed LDO regulator are low voltage (LV) MOSFETs, hence saving the high voltage devices fabrication cost required in a conventional design. Two LV power transistors are cascaded in the power train. A mid-rail regulator is used to generate $1\times V_{DD}$ voltage for the power transistors as well as the main error amplifier to guarantee safe operation. The mid-rail regulator employs stacking transistors to handle the high supply voltage. Moreover, Miller compensation with adaptive biasing is used to achieve good stability and fast transient response. A proof-of-concept design is fabricated in a standard 0.18-$\mu$m CMOS process which achieves 3.3–3.6V nominal input, 3.1V nominal output and 100mA loading capability with all the transistors being 1.8V MOSFETs.

This work presents a fully integrated mixed-mode low-dropout voltage regulator that achieves a fast transient response by utilizing two feedback mechanisms. The first feedback mechanism is the conventional analog regulation that includes an operational amplifier. The second feedback mechanism is based on digitizing any fast change in the output voltage using multiple comparators and subsequently enabling either an NMOS-based or a PMOS-based current DAC. The DAC provides current in opposite polarity to the sharp transient change in load current. As a result, addressing sharp changes in load current is not limited by the gain–bandwidth product of the error amplifier. The LDO was implemented using 180-nm CMOS technology devices. It uses a supply voltage input range of 1.6–2V and produces an output voltage of 1.2V. In simulations, the LDO regulator achieves 143-$\mu$ A quiescent current, $-$56-dB PSRR @ 1-kHz noise frequency and an output voltage drop of around 200mV for a load current step of 100mA. The LDO can provide a maximum load current of 200mA.