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It is anticipated that the downsizing of the CMOS device will end soon, but Moore’s law will continue for several more generations. In recent technology nodes, the performance improvement and higher density of CMOS integrated circuits depended on the smaller footprint resulting from a larger fin height of FinFETs. As device scaling approaches its end, every possible method to increase chip density has been extensively explored. These include the introduction of nanosheet or forksheet structures, better arrangement of power rails and three-dimensional stacking technologies from the device level to the system level. In this review, we highlight various strategies for extending Moore’s law. We discuss the challenges of nanosheet transistors, which are believed to be the ultimate MOS structure and will be implemented in the next technology node. We also discuss some alternative ultimate MOS structures. Nevertheless, from the technological and economic points of view, the mainstream technology in the coming decades should be 3D stacking technology such as CFET at the device level and monolithic 3D technology for system integration.

Under the auspices of Defense Advanced Research Project Agency's Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology, simulations and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS 5HP (50 GHz f_T HBTs with 0.5 μm CMOS) and 7HP (120 GHz f_T HBTs with 0.18 μm CMOS) technologies will be presented.

This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that V_T matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials (Ge, diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

This paper describes the recent advancements in the development of nanoelectronic SONOS nonvolatile semiconductor memory (NVSM) devices and technology, which are employed in both embedded applications, such as microcontrollers, and 'stand-alone', high-density, memory applications, such as cell phones and memory 'sticks'. Multi-dielectric devices, such as the MNOS devices, were among the first NVSM; however, over the ensuing years the double polysilicon, floating-gate device has become the dominant semiconductor NVSM technology. Today, however, questions arise as to future scaling and cost effectiveness of floating gate technology – questions, which have sparked renewed interest in SONOS technology. The latter offers a single polysilicon device structure with reduced lithography steps together with compact cell layouts - compatible with 'standard' CMOS technology for cost effectiveness. In addition, SONOS technology offers performance features, such as reduced erase and write voltage levels to ease the design of peripheral memory circuits with a decrease in electric fields and localized charge storage for improved reliability and multi-bit storage, and ease of memory testing. A special feature of SONOS technology is radiation hardness, which makes this technology ideal for advanced Space and Military systems. SONOS devices use ultra-thin tunnel oxides (2nm) and operate with 'modified' Fowler-Nordheim and 'direct' tunneling in both erase and write (program) modes. A thicker tunnel oxide SONOS device (5nm), called the NROM™ device, uses 'hot electron injection for programming and 'hot hole band-to-band tunneling' for erase. The NROM™ device provides spatially isolated, two-bit storage with the possibility of multi-level charge (MLC) storage at each bit location. This paper describes the physical electronics for these device structures and their erase/write, retention and endurance characteristics. In addition, several novel SONOS device structures are discussed as potential candidates for future NVSM.

Scaling of complementary metal oxide semiconductor (CMOS) technologies to the sub-100 nm dimension regime increase the sensitivity to pervasive terrestrial radiation. Diminishing levels of charge associated with information in electronic circuits, interactions of multiple transistors due to tight packing densities, and high circuit clock speeds make single event effects (SEE) a reliability consideration for advanced electronics. The trend to adapt and apply commercial IC processes for space and defense applications has provided a catalyst to the development of infrastructure for analysis and mitigation that can be leveraged for advanced commercial electronic devices. In particular, modeling and simulation, leveraging the dramatic reduction in computing cost and increase in computing power, can be used to analyze the response of electronics to radiation, to develop and evaluate mitigation approaches, and to calculate the frequency of problematic events for target applications and environments.

The feasibility of CMOS circuits operating at frequencies in the upper millimeter wave and low sub-millimeter frequency regions has been demonstrated. A 140-GHz fundamental mode VCO in 90-nm CMOS, a 410-GHz push-push VCO in 45-nm CMOS, and a 180-GHz detector circuit in 130-nm CMOS have been demonstrated. With the continued scaling of MOS transistors, 1-THz CMOS circuits will be possible. Though these results are significant, output power of signal generators must be increased and acceptable noise performance of detectors must be achieved in order to demonstrate the applicability of CMOS for implementing practical terahertz systems.

A CMOS cascode amplifier, biased near the threshold voltage of a MOSFET, for terahertz direct detection is proposed. A CMOS terahertz imaging circuit (size: 250 × 180 ìm) is designed and fabricated on the basis of low-cost 180-nm CMOS process technology. The imaging circuit consists of a microstrip patch antenna, an impedance-matching circuit, and a direct detector. It achieves a responsivity of 51.9 kV/W at 0.915 THz and a noise equivalent power (NEP) of 358 pW/Hz^1/2 at a modulation frequency of 31 Hz. NEP is estimated to be reduced to 42 pW/Hz^1/2 at 100 kHz. These results suggest that cost-efficient terahertz imaging is possible in the near future.

The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

A low-power and low-data-rate (100 kbps) fully integrated CMOS impulse radio ultra-wideband (IR-UWB) transmitter for biomedical application is presented in this paper. The transmitter is designed using a standard 180-nm CMOS technology that operates at the 3.1-5 GHz frequency range with more than 500 MHz of channel bandwidth. Modulation scheme of this transmitter is based on on-off keying (OOK) in which a short pulse represents binary “1” and absence of a pulse represents binary “0” transmission. During the ‘off’ state (sleep mode) the transmitter consumes only 0.4 μW of power for an operating voltage of 1.8 V while during the impulse transmission state it consumes a power of 36.29 μW. A pulse duration of about 3.5 ns and a peak amplitude of the frequency spectrum of about -47.8 dBm/MHz are obtained in the simulation result which fully complies with Federal Communication Commission (FCC) regulation.

A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.

Digital-to-analog converter (DAC) is a part of various biomedical signal processing systems. DAC is one of the essential blocks optimizing the performance of various analog-to-digital converters (ADCs) such as SAR-ADC, Delta-Sigma ADC. In this paper, a 16-bit DAC is designed and analyzed that can be used in various applications of ADCs specifically useful in effective biomedical data processing. A design of resistor-2 resistor (R-2R) type DAC based on binary weighted resistors is implemented using 16-bit resolution at sampling rate of 500 MS/s. The main components of the design are R-2R ladder, Switch and operational amplifier. During the design of R-2R DAC op-amp, a current mirror circuit is used that provides a single-ended voltage signal without having any losses. In addition to that, it also uses RC coupling for blocking the DC part of the signal and improves the closed loop stability. All the work was carried out by using cadence virtuoso editor tool. The DAC is designed and simulated at 90 and 45 nm CMOS technology and a comparative analysis is done. The result obtained matches the desired specifications of DAC and it is more efficient and can be used for high-speed applications.

GaN-based solutions can handle emerging technological demands from today’s fast-changing electronics industry. AlGaN/GaN heterostructures offer the possibility of a variety of applications. The primary issues in commercializing GaN-based technology are reliability and performance enhancement. This research focuses on recent improvements in AlGaN/GaN-based high-electron-mobility transistors (HEMTs) for diverse high-speed applications. This review will assist researchers in gathering all relevant knowledge on AlGaN/GaN HEMT structure in one location, allowing them to focus on developing high-speed applications.

This paper introduces a device performance optimization approach for the FinFET through optimization of the gate length. As a result of reducing the gate length, the leakage current (I${}_{\mathrm{\text{off}}}$) increases, and consequently, the stress along the channel enhances which leads to an increase in the drive current (I${}_{\mathrm{\text{sat}}}$) of the PMOS. In order to sustain I${}_{\mathrm{\text{off}}}$, work function is adjusted to offset the effect of the increased stress. Changing the gate length of the transistor yields different drive currents when the leakage current is fixed by adjusting the work function. For a given device, an optimal gate length is found to provide the highest drive current. As an example, for a standard performance device with I${}_{\mathrm{\text{off}}}$ = 1 nA/um, the best performance I${}_{\mathrm{\text{sat}}}$ = 856 uA/um is at L = 34 nm for 14 nm FinFET and I${}_{\mathrm{\text{sat}}}$ = 1130 uA/um at L = 21 nm for 7 nm FinFET. A 7 nm FinFET will exhibit performance boost of 32% comparing with 14 nm FinFET. However, applying the same method to a 5 nm FinFET, the performance boosting is out of expectance comparing to the 7 nm FinFET, which is due to the severe short-channel-effect and the exhausted channel stress in the FinFET.

This paper presents a digital MEMS gyroscope with 40${}^{\circ }$/h instability variation in −40${}^{\circ }$C to 85${}^{\circ }$C, performing 5${}^{\circ }$/h instability variation at normal temperature and 0.01% nonlinearity in the range of ±400${}^{\circ }$/s. This stability was achieved by using temperature compensation for the zero-output value changed after the temperature signal. As the resonant frequency of the mechanical structure varied according to the temperature linearly, a frequency calculator was adopted to detect the temperature of the mechanical structure. And the resolution of the frequency could be up to 0.01 Hz with a 1 MHz clock frequency used, obtaining a 10 Hz bandwidth. The driving mode used a PI controller to control a VGA to maintain at a fixed effective value of the driving signal. The sensing mode contained a low noise C/V convertor and a switch demodulation, which could give the angular velocity signal to the A/D convertor. Then the output data of A/D will be compensated in the digital domain. Finally, the digital output of the gyroscope will be available through a normal SPI serial port. The whole circuit was realized on one chip with an active circuit area of 3.5 mm × 5.2 mm fabricated in a 0.35 $\mu$m CMOS technology. And the MEMS structure and circuit are packaged in a 2.5 cm × 2.5 cm × 2.5 cm aluminum mold. The digital output of the gyroscope earned a noise floor of 0.0024${}^{\circ }$/s.

This paper presents a novel digital silicon gyroscope interface circuit, designed by 0.35 $\mu$m BCD process, and the chip area is 4.8 mm ∗ 5.0 mm. The traditional noise model of charge amplifier decomposes the noise into voltage noise and current noise. But the test results show that current noise accounts for a large proportion, which is not consistent with the theoretical model. Through the analysis of experimental data and the study of operational amplifier’s working principle in charge amplifier, a new noise model is established, which makes the experimental data closer to the theoretical model. The design makes use of the bandpass characteristics of the bandpass sigma–delta modulator consistent with the sensitive structure of the silicon gyroscope, and optimizes the digital principle of the silicon gyroscope. The digital demodulation of bandpass sigma–delta modulator (BP SDM) can directly separate the in-phase component from the orthogonal component, which eliminates the tedious design of carrier signal digitization and multi-digital filtering, simplifies the frame structure of the whole digital silicon gyroscope system and reduces the design difficulty and physical cost. The ASIC of silicon gyroscope digital interface circuit is tested in combination with the sensitive structure. The noise density of 0.0014${}^{\circ }$/s/Hz${}^{1/2}$, zero stability of 1${}^{\circ }$/h (1$\sigma$) and 0.2${}^{\circ }$/h (Allen variation). The test of ASIC and the whole machine proves the correctness of the theoretical model, which reflects the correctness of the performance of the digital interface circuit of silicon gyroscope.

The high leakage current in deep submicron regimes is becoming a significant contributor to the power dissipation of CMOS circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power, especially in the low power applications. This paper explores the various transistor intrinsic leakage mechanisms including the weak inversion, the drain-induced barrier lowering, the gate-induced drain leakage, and the gate oxide tunneling.

This paper proposes several improved CMOS analog integrated circuits for fuzzy inference system as the general modules, including voltage-mode implementations of minimization circuit, programmable Gaussian-like membership function circuit, and centroid algorithm normalization circuit without using division. A two-input/one-output fuzzy system composed of these circuits is implemented and testified as a nonlinear function approximator. HSPICE simulation results show that the proposed circuits provide characteristics of high operation capacity, simple inference, low power dissipation, and high precision.

The lumped capacitance model, which ignores the existence of wire resistance, has been traditionally used to estimate the charging and discharging power consumption of CMOS circuits. We show that this model is not correct by pointing out that MOSFETs consume only part of the energy supplied by the source. During this study, it was revealed that about 20% of the power is consumed in the wire resistance of the buffered global interconnect, when the interconnect is modeled with RC tree networks. The percentage goes up to 30 when RLC model is used indicating the importance of inductance in interconnect model for power estimation. For RLC networks, we propose a compact yet very accurate power estimation method based on a model reduction technique.

This paper presents a low power CMOS analog integrated circuit of a Takagi–Sugeno fuzzy logic controller with voltage/voltage interface, small chip area, relatively high accuracy and medium speed, which is composed of several improved functional blocks. Z-shaped, Gaussian and S-shaped membership function circuits with compact structures are designed, performing well with low power, high speed and small areas. A current minimization circuit is provided with high accuracy and high speed. A follower-aggregation defuzzification block composed of several multipliers for center of gravity (COG) defuzzification is presented without using a division circuit. Based on these blocks, a two-input one-output singleton fuzzy controller with nine rules is designed under a CMOS 0.6 μm standard technology provided by CSMC. HSPICE simulation results show that this controller reaches an accuracy of ±3% with power consumption of only 3.5 mW (at ±2.5 V). The speed of this controller goes up to 0.625M Fuzzy Logic Inference per Second (FLIPS), which is fast enough for real-time control.