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Security of cryptographic circuits is a major concern. Smartcards are targeted by sophisticated attacks like fault attacks that combine physical disturbance and cryptanalysis. We propose a methodology and a tool (PAFI) to analyze the robustness of circuits under fault attacks using fault injection in simulation. The number of injections is reduced by taking into account the function of the latches in the whole circuit. We tested a circuit implementing the cryptosystem AES and showed that our approach reduces the number of fault injections to be performed (- 80%). Moreover, most of the selected injection points are the ones that lead to known fault attacks (95%).

Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.

One of the interesting features of software systems is that a large number of soft-errors are inherently derated (masked) at the software level. The rate of error-deration may depend on the inherent features of design and programming structures used in the software. This paper investigates the inherent effects of different programming structures on the program resiliency; to this end, six different benchmark programs were implemented by four different programming methods and structures. Profiling experiments were performed on the benchmarks to identify those features of the programming structures that affect the rate of error-deration; then, in order to quantify and examine the inherent resiliency of the programming structures, about 6,720,000 faults were injected into the benchmark programs. The results reveal that about 42.67% of faults in the programs implemented based on while loop-structure are derated; this figure for the programs implemented based on do-while, for and recursive structures are respectively 42.18%, 40.22% and 31.66%. The programs based on the while loop-structure have about 11.01% higher resiliency than the recursive programs. These results can enable software designers to select the most resilient loop-structures for developing inherently resilient programs.

Decreasing the scale of transistors and exponential increase in the transistor counts has made the soft-errors as one of the major causes of software failures. Fault injection is a powerful method for dependability assessment of a computer system against soft-errors. A considerable number of randomly injected faults in the current methods and tools are effect-less or equivalent. To overcome this problem and reduce the cost of fault injection, this study presents a software based fault-injection method that accurately evaluates the dependability of a computer system with a limited number fault-injection. Using a genetic algorithm (GA) the most vulnerable executable paths of an input program is identified; then only the basic blocs (BBs) into the identified vulnerable paths are considered as the target of fault injection. The results of fault injections on the set of 8 traditional benchmark-programs show that the proposed method reduces about 20% of effect-less faults by avoiding the injection of faults in the error-derating blocks of a program. Furthermore, the number of injected faults is reduced to 60% of its original size in the random injection. Also, the proposed method provides more stable and accurate results than the random injection.

An integrated framework for Virtual Verification and Validation (VVV) for a complete automotive system is proposed. The framework can simulate/emulate the system on three levels: System on Chip (SoC), Electronic control unit (ECU) and system level. The framework emulates the real system including hardware (HW) and software (SW). It enhances the automotive V-cycle and allows co-development of the automotive system SW and HW. The procedure for debugging AUTOSAR application on the virtual platform (VP) is shown. SW and HW profiling is feasible with the presented methodology. Verification and validation of automotive embedded SW is also presented. The proposed methodology is efficient as the system complexity increases which shortens the development cycle of automotive system. It also provides fault injection capability. With HW emulation, co-debugging mechanism is demonstrated. A case study covering the framework capability is presented. The case study demonstrates the proposed framework and methodology to design, simulate, trace, profile and debug AUTOSAR SW using VPs.

Critical constituent gates are first detected and graded based on their individual impact of an error in the outputs. This brings in the idea of practical reliability analysis metric. Then, the approximation of arithmetic circuits by random logic applied to least significant gates is introduced. The 74283 fast adder is used as an example to illustrate the feasibility of the proposed methods. Simulation results show the potential efficient application of the proposed reliability analysis metric and approximation method.

We propose a safety-oriented design process for IP-based safety-critical system-on-chip (SoC). The proposed safety process can facilitate the measurement of the robustness based on the safety-related metrics and scales of failure-induced risks in a system that can be employed to locate the critical components for protection to effectively diminish the influence of failures on the system. The risk reduction phase is activated to enhance the robustness of critical components identified by vulnerability analysis if the measured robustness is insufficient. An SoC-level safety design platform was built on the SystemC Synopsys Platform Architect MCO to demonstrate the core idea of the safety process. The safety-oriented design process for an ARM-embedded SoC modeled at the TLM level was conducted to demonstrate the feasibility of our safety approach.

The performance of electrical connectors can be significantly impacted by periodic variations in contact resistance caused by vibrational stress. Intermittent faults resulting from such stress are characterized by their random and fleeting nature, making it difficult to study and replicate them. This paper proposes a novel method for reproducing intermittent faults in electrical connectors. To implement this method, intermittent fault data are first collected from electrical connectors subjected to different vibration loads. Next, a statistical distribution model is constructed using kernel density estimation (KDE). Based on this model, a fault injector is designed to simulate intermittent faults under varying vibration loads. The simulated faults are then compared to real-world intermittent fault signals in a controlled environment to validate the accuracy of the method. The results demonstrate that the proposed method effectively reproduces intermittent faults in electrical connectors under varying vibration conditions. This approach can be used to better understand the behavior of connectors under vibrational stress and to develop more effective testing and fault diagnosis methods.

Generating faulty data is a key issue in fault injection. The faulty data include not only the ones of extreme values or bad formats, but also the ones which are logically unreasonable. Constraint-based fault injection which negates interface constraints to solve faulty data is effective for logically unreasonable data generation. However, the existing constraint-based approaches just solve brand new data for testing. Such brand new data may easily violate some hidden environment constraints on the test inputs and hence be nonrealistic. Besides, there can be different strategies to negate a constraint in order to derive the constraint-unsatisfied faulty data. What are the possible negation strategies and which strategies are better for high coverage fault injection are still unclear. To these ends, this paper presents a new constraint-based fault injection approach. The approach introduces 10 different strategies for constraint negation and relaxes constraint variables to generate faulty data instead of solving brand new data for fault injection. It can produce faulty data which are closer to the original non-faulty ones and hence likely to be more realistic. We experimentally investigated the effectiveness and cost of the introduced constraint negation strategies. The results provide insights for the application of these strategies in fault injection.

In recent years, very long instruction word (VLIW) processor has attracted much attention in that it offers a high instruction level parallelism and reduces the hardware design complexity. In this paper, we present two fault-tolerant schemes for VLIW processors. The first one is termed as test-instruction scheme which is based on the concept of instruction duplication to detect the errors. The process of test-instruction scheme consists of the error detection, error rollback recovery and reconfiguration. The second approach is called self-checking scheme which adopts the concept of self-checking logic to detect the errors. A real-time error recovery procedure is developed to conquer the errors. We implement the proposed designs of fault-tolerant VLIW processor in VHDL and employ the fault injection and fault simulation to validate our schemes. The main contribution of this research is to present the complete frameworks from error detection to error recovery for fault-tolerant design of VLIW processors. Experience learned from this investigation is that the issues of error detection and error recovery entail considering together. Without taking both issues into account simultaneously, the outcomes may lead to the improper conclusions.

Software play remarkable roles in different critical applications. On the other hand, due to the shrinking of transistor size and reduction in supply voltage, radiation-induced transient errors (soft errors) have become an important source of computer systems failure. As the rate of transient hardware faults increases, researchers have investigated software techniques to control these faults. Performance overhead is the main drawback of software-implemented methods like recovery blocks that use technical redundancy. Enhancing the software reliability against soft errors by utilizing inherently error masking (invulnerable) programming structures is the main goal of this study. During the programming phase and at the source code level, programmers can select different storage classes such as automatic, global, static and register for the data into their program without paying attention to their inherent reliability. In this study, the inherent effects of these storage classes on the program reliability are investigated. Extensive series of profiling and fault-injection experiments were performed on the set of benchmark programs implemented with different storage classes. Regarding the results of experiments, we find that the programs implemented with automatic storage classes have inherently higher reliability than the programs with static and register storage classes without performance overhead. This finding enables the programmers to develop highly reliable programs without technical redundancy and performance overhead.

We propose a systematic approach for design and validation of error detection software. Formally, the semantic of a specification is represented by a transition system. This representation is then used to generate a flowgraph or ddgraph which is used to construct an execution path tree. The information obtained from this algorithm representation is used to aid in the design of software-based fault detection techniques for hardware faults.

Flowgraph and ddgraph representations provide information to predict future program flow. During execution, the current program path is recorded, along with the expected path. Checks are placed to verify that the program path follows the predicted path.

Algorithm-based fault tolerance (ABFT) techniques are used to detect data structure corrupting faults and to improve the fault coverage. Fault coverage provided by this approach for different types of hardware faults has been estimated through experiments with the software-based fault injection tool (SOFIT) and the data is presented to demonstrate the effectiveness of the method.

Reliability and fault tolerance are important metrics for evaluating the performance of Wireless Sensor Network (WSN). Although many WSN protocols have performed well in laboratory and simulation circumstances, the complex environment during actual deployment can lead to some problems, such as system abnormal, communication interruption, packet loss and reliability decline. These make it difficult to debug and perform failure analyses on the system. In this paper we present a new method of injecting faults to WSN artificially. By simulating the scene interference and observing the change of network, we can evaluate the reliability and fault tolerance of the network. We can also find a way to improve the network performance by analyzing the change of network after injection of faults. This system includes fault inject node and failure analysis software. The fault inject node can inject practical faults and interference which the WSN is likely to encounter, and can receive the WSN nodes' data and store them. The failure analysis software can analyze data obtained from the fault inject nodes, and display the topology change to evaluate reliability. Using pairs of WSN node and fault injection performance evaluation system (FIPES) node, we evaluate this system in a five-storey office. This includes the use of FIPES to inject large-scale faults into WSN and monitor the network fault response conditions, thereby verifying the effect of FIPES fault injection. Experimental results show that the FIPES can inject various kinds of faults into WSN effectively, and can evaluate WSN performance metrics such as reliability, packet loss rate etc.

Sandal is a modeling language designed for specifying and model-checking fault-prone message-passing systems. The language supports the modular description of typical faults including unexpected termination of processes, random loss of messages and timeout. Thus on defining a model in Sandal, one does not need to write such faulty actions explicitly intermingled with the primary behaviors of the model. The compiler of the language automatically weaves them and produces a set of NuSMV modules. This paper describes how the weaving mechanism works and demonstrates the usefulness of the language using an example.

Testability is a characteristic of a system or a device to check its status and isolate its inner faults. To check whether the testability meets the requirement before acceptance, testability demonstration is usually conducted by injecting faults into the equipment. However, with the increasing scale and integration of the equipment system, manual testability demonstration takes too much time and man power. To automate the process of the testability demonstration and overcome the data share obstacles, this paper proposed a testability-demonstration software platform based on fault injection. For ten years, our ATS software VITE (Virtual Instrument Test Environment) has been widely used in the aircraft industry. Based on the software, a testability demonstration software platform is proposed to automate the testability demonstration process and realize data sharing. The platform includes the fault sample allocation software (FSAS), the master control software (MCS), the fault injection software (FIS), and the data monitor software (DMS). The practical application has proved that the software platform is able to decline the test time and improve the efficiency significantly.