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Noise Bus Modeling in Network on Chip

Moez Balti

Telecom Department, Tunisian High Institute in Telecom Applications (Iset’Com), Pôle Technologique cité elghazella, Ariana, 2083/Tunis, Tunisia

E-mail Address: moez_balti@yahoo.fr

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https://doi.org/10.1142/S0218126618501499Cited by:1 (Source: Crossref)

Abstract

This paper considers the noise modeling of interconnections in on-chip communication. We present an approach to illustrate modeling and simulation of interconnections on chip microsystems that consist of electrical circuits connected to subsystems described by partial differential equations, which are solved independently. A model for energy dissipation in RLC mode is proposed for the switching current/voltage of such on-chip interconnections.

The Waveform Relaxation (WR) algorithm is presented in this paper to address limiting in simulating NoCs due to the large number of coupled lines.

We describe our approach to the modeling of on-chip interconnections. We present an applicative example of our approach with VHDL-AMS implementations and simulation results. This article analyzes the coupling noise, the bit error rate (BER) as well as the noise as a function of the rise/fall time of the signal source which can significantly limit the scalability of the NoCs.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

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