Journal of Circuits, Systems and Computers

A PLL-based clock generator with an auto-calibration circuit is presented. The auto-calibration circuit employs an oscillator-based time-to-digital converter (TDC) to achieve a constant loop bandwidth and fast lock time. The TDC measures the operating frequency of $M$-stage ring-VCO with a resolution of $f_{\mathrm{\text{REF}}}∕(k\cdot 2M)$ in a time period of $k\cdot T_{\mathrm{\text{REF}}}$. The measured frequency is utilized to calibrate loop bandwidth and VCO frequency. The clock generator is designed in 40nm CMOS process and operates from 1.2GHz to 3.6GHz with 8-phase outputs. The total lock time is less than 3$\mu$s including calibration and PLL closed-loop locking processes. Operating at 3.2GHz, the in-band phase noise is better than $-99.4$dBc/Hz and root-mean square (RMS) jitter integrated from 10KHz to 100MHz is 2 ps. In the entire operating range, the RMS jitter and reference spur are better than 5.5ps and $-68.5$dBc/Hz, respectively. The clock generator consumes only 3mW from 1.1V supply at high-frequency end and 1.6mW at low-frequency end. The active area is only 0.04mm² including on-chip loop filter and auto-calibration circuits.

This paper addresses throughput improvement in millimeter-wave (mmWave) mesh networks via two novel distributed scheduling algorithms. The first one uses packet aggregation and block acknowledgment (ACK) that were introduced in the IEEE Std 802.11e-2005 for WiFi. Specifically, a distributed time-division multiplexing scheduling algorithm, which targets increasing the network capacity via reserving as many contiguous slots as possible for each node, is proposed thus enabling packet aggregation. This algorithm achieves its goal when the operating signal-to-noise ratio (SNR) is significantly high. If that is not the case, the second proposed algorithm can be used. It is a distributed one that starts initially with a random feasible schedule determined cooperatively between nodes. The algorithm then tries to reach better feasible schedules via parallel and successive local searches without violating feasibility constraints. Extensive simulations show that the first algorithm improves the network throughput by almost $70\%$ compared to the well-known memory-guided directional medium access control (MDMAC) due to reducing the transmission overhead. The second proposed algorithm is shown to increase the number of reserved slots by about $6\%$ over MDMAC. Both algorithms are shown to either increase or almost maintain the same degree of fairness among the nodes as quantified by Jain’s fairness index.

In this paper, the design methodology of a parallel-resonant $LC$ converter for fuel cell applications in the electric vehicle is proposed in order to achieve high efficiency. Although the converter is unidirectional, it is interposed between the fuel cell and the DC link. Additionally, the converter is made up of two full bridges, an $LC$ resonant filter and a planar transformer. The use of a high-frequency transformer enables to minimize the converter size and the weight, to produce a higher voltage in the secondary side from an input voltage (fuel cell) and to isolate the full bridges. Furthermore, the rectifier diodes operate with a zero-current switching. Therefore, an experimental converter prototype has been designed, simulated, built and tested in the laboratory. Finally, a prototype having 30V as an input and 150V as an output with 500W is designed to demonstrate and analyze the proposed converter.

A high-efficiency pulse-frequency modulation (PFM) boost DC–DC converter with adaptive on-time (AOT) control method is proposed. A novel three-step startup procedure is proposed and applied on the boost converter, which makes the converter start up with a below-threshold voltage. Besides, adaptive on-time control method can reduce the output ripple dramatically. The proposed integrated boost converter is designed in an SMIC 0.18-$\mu$m standard CMOS process and occupied a chip area of $1.5\times 1.4$mm² without any low-$V_t$ MOSFETs. In the adopted process, the threshold voltages of PMOS and NMOS are $-$0.45V and 0.48V, respectively. The simulation results show that the proposed converter can start up successfully at the input voltage of 0.25V, the output voltage is 1.8V with the ripple less than 33mV, and the peak efficiency can be up to 94.7%.

Recent research has demonstrated the effectiveness of deep subspace learning networks, including the principal component analysis network (PCANet) and linear discriminant analysis network (LDANet), since they can extract high-level features and better represent abstract semantics of given data. However, their representation does not consider the nonlinear relationship of data and limits the use of features with nonlinear metrics. In this paper, we propose a novel architecture combining the kernel collaboration representation with deep subspace learning based on the PCANet and LDANet for facial expression recognition. First, the PCANet and LDANet are employed to learn abstract features. These features are then mapped to the kernel space to effectively capture their nonlinear similarities. Finally, we develop a simple yet effective classification method with squared ${\ell }_2$-regularization, which improves the recognition accuracy and reduces time complexity. Comprehensive experimental results based on the JAFFE, CK$+$, KDEF and CMU Multi-PIE datasets confirm that our proposed approach has superior performance not just in terms of accuracy, but it is also robust against block occlusion and varying parameter configurations.

We present an analytical approach that is based on nonlinear programming to perform VLSI standard cell placement. Our method first clusters a netlist to reduce the number of cells and then performs quadratic optimization on the reduced netlist. Finally, it uses Nesterov’s method for solving nonlinear equations for the problem. The framework of our tool, Kapees3, is scalable and generates high quality results. The experimental results for Peko Suite 1 and Peko Suite 2 benchmarks show promising improvements. Our placement tool outperforms NTUPlace3, Dragon, Feng Shui, Capo10.5, by 46%, 57%, 48% and 25%, respectively, on PEKO Suite 1. For PEKO Suite 2, our placement tool outperforms NTUPlace3, Dragon, Feng Shui, Capo10.5 and mPL6 by 30%, 47%, 57%, 69% and 2.7%, respectively. On MMS benchmarks, we obtain wirelength improvement over Capo10.5 by 56.62%, FLOP by 7.84%, FastPlace by 11.55%, ComPLx by 4.58%, POLAR by 23.67%, mPL6 by 9.96% and NTUPlace3-Unified by 2.96%.

This paper deals with a novel method for Bat Algorithm (BA) based on optimal tuning of Fractional-Order Proportional Integral Derivative (FOPID) controller for governing the rotor speed of sensorless Brushless Direct Current (BLDC) motor. The BA is used for developing a novel optimization algorithm which can generate five degrees of freedom parameters namely $K_p$, $K_i$, $K_d$, $\lambda$ and $\mu$ of FOPID controller. The desired speed control and robust performance are achieved by using the FOPID closed loop speed controller with the help of BA for optimal tuning. The time domain specifications of a dynamic system for unit step input to FOPID controller for speed response such as peak time ($t_r$), Percentage of overshoot (PO), settling time ($t_s$), rise time ($t_r$) have been evaluated and the steady-state error ($e_{\mathrm{\text{ss}}}$) of sensorless speed control of BLDC motor has been measured. The simulation results are compared with Artificial Bee Colony (ABC) optimization method and Modified Genetic Algorithm (MGA) for evaluation of transient and steady state time domain characteristics. The proposed BA-based FOPID controller optimization technique is more efficient in improving the transient characteristic performance and reducing steady state error.

The growing demand for high-performance digital circuits, mainly involving FPGAs, increases the demand for high-level synthesis (HLS) tools. Traditional Hardware Description Languages (HDLs) are complex and depend on low-level abstractions, thereby requiring hardware detailed knowledge from developers. In turn, the current HLS tools are based on proprietary or C/C$++$ derived languages, which allow easier circuit description but decrease performance. This work presents an alternative solution for designing digital circuits, which arises from the Notification-Oriented Paradigm (NOP). The NOP is an alternative computing solution based upon a set of predefined interconnected entities whose collaborations are performed through precise notifications. The NOP, when targeted to digital hardware (DH), allows the developer to describe the circuit behavior just by connecting and parameterizing elements. The result is a VHDL file that can be compiled for any platform from any manufacturer. In order to check the functionality of this approach, sorting circuits were built both with usual VHDL and with the NOP VHDL aiming to compare the resulting circuits in terms of operating frequency and resource use. The results show that the NOP VHDL approach facilitates the build of digital circuits when compared to the VHDL usual approach without limiting the operating frequency or increasing the use of resources.

Adaptive filters have wide range of applications in areas such as echo or interference cancellation, prediction and system identification. Due to high computational complexity of adaptive filters, their hardware implementation is not an easy task. However, it becomes essential in many cases where real-time execution is needed. This paper presents the design and hardware implementation of a variable step size 40 order adaptive filter for de-noising acoustic signals. To ensure an area efficient implementation, a novel structure is being proposed. The proposed structure eliminates the requirement of extra registers for storage of delayed inputs thereby reducing the silicon area. The structure is compared with direct-form and transposed-form structures by adapting the filter coefficients using four different variants of the least means square (LMS) algorithm. Subsequently, the filters are implemented on three different field programmable gate arrays (FPGAs) viz. Spartan 6, Virtex 6 and Virtex 7 to find out the best device family that can be used to implement an Adaptive noise canceller (ANC) by comparing speed, power and area utilization. The synthesis results clearly reveal that ANC designed using the proposed structure has resulted in a reduction in silicon area without incurring any significant overhead in terms of power or delay.

The main memory system has become crucial not only because it has to meet an increasing bandwidth requirement, but also because it has to seamlessly support many concurrently executing applications. In order to improve memory performance, a memory controller with efficient arbitration is necessary. It is well known that memory performance is dependent on the memory access patterns. The offline performance analysis has difficulty analyzing the Dynamic Random Access Memory (DRAM) performance accurately because a huge set of trace patterns is needed. This paper proposes a novel profiler that is synthesized with a memory controller in order to monitor and analyze the memory controller performance at runtime. In this paper, five key metrics for performance evaluation are defined and they are monitored and evaluated at runtime by the proposed profiler. A prototype system with a processor core, a memory controller, DRAM modules, and peripheral devices are implemented on a field-programmable gate array (FPGA) board to carry out the experiments. It has been observed that the worst latency overhead differs for each benchmark. In addition, a new overall overhead estimation method is proposed to estimate the memory access latency overhead in time, and this method can be used to evaluate the performance of a certain memory arbitration method depending on running applications.

In this paper, a high performance single-phase modified bridgeless AC–DC converter with reduced switch voltage stress for power factor correction (PFC) is introduced. The proposed converter is based on a single-ended primary-inductance converter (SEPIC) to meet the demands of PFC to unity and output voltage regulation. To reduce the number of components, the input bridge is combined with the SEPIC converter since the conventional SEPIC PFC is suffering with high conduction losses. It offers many advantages, such as fewer semiconductor devices in current flowing path which lead to improve the thermal management, low stress on each component, improved efficiency, high power factor compared to classical converter. Detailed analysis and design equations of the converter are presented. Simulation and experimental results are discussed for a 300W prototypeunder the universal input voltage (85–235V) to validate the performance of the converter.

This paper exploits the CMOS beta multiplier circuit to synthesize a temperature-independent voltage reference suitable for low voltage and ultra-low power biomedical applications. The technique presented here uses only MOS transistors to generate Proportional To Absolute Temperature (PTAT) and Complimentary To Absolute Temperature (CTAT) currents. A self-biasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65nm CMOS has been developed and occupies 0.0039mm², and at room temperature, it generates a 204mV reference voltage with 1.3mV drift over a wide temperature range (from $-$40${}^{\circ }$C to 125${}^{\circ }$C). This has been designed to operate with a power supply voltage down to 0.6V and consumes 1.8uA current from the supply. The simulated temperature coefficient is 40ppm/${}^{\circ }$C.

This paper presents an efficient approach to design wideband, accurate, stable, and minimum-phase fractional-order digital differentiators (FODDs) in terms of the infinite impulse response (IIR) filters using an evolutionary optimization technique called flower pollination algorithm (FPA). The efficiency comparisons of FPA with real-coded genetic algorithm (RGA), particle swarm optimization (PSO), and differential evolution (DE)-based designs are conducted with respect to different magnitude and phase response error metrics, parametric and nonparametric statistical hypotheses tests, computational time, and fitness convergence. Exhaustive simulation results clearly demonstrate that FPA significantly outperforms RGA, PSO, and DE in attaining the best solution quality consistently. Extensive analysis is also conducted in order to determine the role of control parameters of FPA on the performance of the designed FODDs. The proposed FPA-based FODDs outperform all the designs published in the recent literature with respect to the magnitude responses and also achieve a competitive performance in terms of the phase response.

This paper introduces a new technique to design an analog MOS switch to be used in sampled-data circuits. In any sampled-data system, the accuracy of the sampling switch is a critical parameter to determine the overall performance of the system. To satisfy accuracy requirements of the switch, a novel technique to reduce channel charge injection error is proposed. The proposed switch has a very simple structure and it uses a small area of the chip. Also, it has a low on-resistance and its variation over the input signal range is acceptable. In order to evaluate the performance of the proposed switch, simulations are done in a 0.18$\mu$m standard CMOS technology. Simulation results show that the sampling errors produced by the channel charge injection is eliminated through a cancellation technique using an auxiliary transistor. The output error charge due to charge injection over a wide range of the input signal variation is very low (less than 1.45fC). Also, simulation results show that the proposed switch achieves signal-to-noise plus distortion ratio (SNDR) of 85.05dB, effective number of bits (ENOB) of 13.83, total harmonic distortion (THD) of $-$87.23dB and spurious-free dynamic range (SFDR) of 88.14dB for a 1MHz sinusoidal input of 800mV peak-to-peak amplitude at 50MHz sampling rate with a 1.8V supply voltage.

This work presents a fully integrated fractional-$N$ frequency synthesizer that covers the entire frequency bands specified in the IEEE 802.11 a/b/g/n. In this paper, the effects of charge pump (CP) gain mismatch on spectral purity of local oscillator signal is studied theoretically and a new high precision self-calibrated CP is presented for alleviating the nonidealities. The idea is implemented in a 0.18-$\mu$m standard CMOS technology. According to post layout simulation, the proposed calibration circuit demonstrates an excellent matching in the CP currents in a wide voltage range. By using this technique, the average of close-in phase noise of the designed frequency synthesizer is suppressed by more than 12dBc. The active whole chip die area is 0.475mm² and the power dissipation from a 1.8-V DC supply is 17.3–20.6mW.

The projected method explains about the problems occurred in the combination of the MEMS switches and the complete scheme plan is resolved through choosing the finest devise limits for the plan. The devise limits, namely, length of beam, width of beam, torsion arm length, switch thickness, holes and gap were measured. At this point, the finest value of the devise limit is forecast by the aid of artificial neural network (ANN). Furthermore, the method contains the optimization method of Gravitational Search Algorithm (GSA) to optimize the input signal and so dropping the Mean Square Error (MSE). The complete scheme is executed in the operational platform of MATLAB and the outcomes were examined.

In software defined radio (SDR) receivers, sample rate conversion (SRC) and channelization are two computational intensive tasks. Coefficient-less cascaded-integrator-comb (CIC) filters achieve SRC with low computational complexity, but the design of its gain droop compensation filter involves coefficients. These coefficients vary with the change in radio standards. In this paper, an architecture for variable digital filter (VDF) for gain droop compensation employing a set of fixed coefficient sub-filters and multi-dimensional polynomials in terms of spectral parameters is realized based on distributed arithmetic (DA). As the coefficients in the sub-filters are fixed, the proposed method uses ROM-based LUTs giving rise to low computational complexity. The proposed DA–VDF filter is synthesized on an application specific integrated circuit (ASIC) employing CMOS 90nm technology using Synopsis Design Complier. The proposed architecture achieves low latency at a reduced area delay product (ADP) of 78% and an efficiency of 72% in energy per sample (EPS) when compared with the conventional MAC-based architecture.