Journal of Circuits, Systems and Computers

This paper presents a planar insert-loaded compact, dual-pole, dual-band, waveguide bandpass filter with adjustable multiple transmission zeros. Two identical inserts are placed on the transverse plane of a standard WR-90 waveguide at 8.41mm distance to achieve the filter characteristics. The insert consists of a stub-loaded C-shaped resonator and two asymmetric slot resonators. Two stub-loaded C-shaped resonators have been used to achieve dual-pole, dual-band response whereas the asymmetric slot pairs have been used to introduce transmission zeros. The structure allows independent control of the center frequencies of the passbands and transmission zeros, which is useful to control the rejection level of out-of-band signals without disturbing the center frequency. Measured result shows a dual-pole, dual-band, bandpass response with center frequencies at 8.81GHz and 10.9GHz, the respective 3dB bandwidths of 0.276GHz and 0.398GHz and transmission zeros at 8.02, 8.5, 9.46, 10.13, 11.53 and 12 GHz.

Recently, an increasing number of real-time systems are implemented on multicore systems. To fully utilize the computation power of multicore systems, the scheduling problem of the real-time parallel task model is receiving more attention. Different types of scheduling algorithms and analysis techniques have been proposed for parallel real-time tasks modeled as directed acyclic graphs (DAG). In this paper, we study the scheduling problem for DAGs under the decomposition paradigm. We propose a new schedulability test and corresponding decomposition strategy. We show that this new decomposition approach strictly dominates the latest decomposition-based approach. Simulations are conducted to evaluate the real-time performance of our proposed scheduling algorithm, against the state-of-the-art scheduling and analysis methods of different types. Experimental results show that our method consistently outperforms other global methods under different parameter settings.

This paper proposes a two-step strategy for designing a variable-bandwidth (VBW) digital filter through minimizing the $L_p$-norm of the magnitude-response error. This $L_p$-norm design can be regarded as a generalized version of the existing weighted-least-squares (WLS) design. Equivalently, the WLS design is a special case of the $L_p$-norm-minimization design for $p=2$. This paper discusses the design of the recursive VBW filter with the transfer function whose denominator is expressed as the product of the second-order sections. As long as all the second-order sections are stable, the recursive VBW filter is also stable. To ensure that the designed recursive VBW filter is stable, we adopt the coefficient-conversion strategy that constrains all the denominator-parameter pairs of the second-order sections within the stability triangle. This paper also proposes a novel conversion function for performing the coefficient conversion. As a consequence, the designed VBW filter is definitely stable. A bandpass VBW filter is designed for showing the feasibility of the $L_p$-norm-minimization-based design and verifying the stability guarantee.

Bandwidth limitation is a vital problem for high-speed data transmission in logging cable telemetry systems (LCTSs). This paper proposes a frequency compensation method with an analog circuit design, possessing high flexibility and robustness. Analytical expressions are derived for the relationship between pole-zero and gain, deviations caused by high temperature; and are then verified via simulation. To address the efficacy of the circuit design, a real case with low computation complexity and high accuracy is proposed and employed. The case of a 7km LCTS shows frequency compensation with a 200% bandwidth expansion — from 160kHz at $-$55dB of the original cable to 300kHz at $-$3dB — and a 60dB improvement in high frequency gain. After comparing the signals with and without compensation, the improvements in transmission performance by the proposed pre-emphasis circuit and equalizer are confirmed.

This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18$\mu$m CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027mm². The overall circuit consumes 9.75$\mu$W from a single 1.5V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80dB input dynamic range (from 10$\mu$V to 100mV), a bandwidth of 4Hz–10kHz, and a total input-referred noise of 5.52$\mu$V.

A low-power, low-supply, low-complexity all-MOSFET voltage reference is implemented in 0.18$\mu$m CMOS process. With the proposed architecture, the number of the transistors can be reduced to the greatest extent. As a result, the supply voltage can not only be decreased to as low as 0.7V, but the power consumption can also be optimized significantly. Simulation results show that the power consumption is 47nW, at a supply of 0.7V. A temperature coefficient (TC) of 42ppm/${}^{\circ }$C is achieved when the temperature ranges from $-$20${}^{\circ }$C to 80${}^{\circ }$C. At room temperature, the voltage reference features a line regulation (LR) of 2.66%/V.

Orthogonal frequency division multiplexing (OFDM) modulation is proposed in 4G wireless communication systems, and is under consideration for the next generation 5G systems. This is due to the higher spectral efficiency (SE) and the better immunity to channel distortions. One of the shortcomings in OFDM is its high peak-to-average power ratio (PAPR). Several schemes have been proposed to reduce the PAPR in OFDM systems. This includes clipping, coding, and pre/post-distortion schemes with or without side information. In this paper, we experimentally demonstrate one of the most promising method, to mitigate the effect of PAPR, entitled the partial orthogonal selective mapping (POSLM). The experimental results show a comparable performance with respect to the simulation results in terms of PAPR reduction, power spectral density (PSD), and bit error rate (BER) metrics.

Image deconvolution is a method for reversing the distortion in an imaging system. It is widely used in removing blur and noise from a degraded image. This is an ill-posed inverse problem, and one should use regularization techniques to solve this problem. Regularization functions play an important role in finding the desired solution. In this paper, a new function in wavelet domain is proposed, which is useful in blind deconvolution. In addition, a simple algorithm is used to obtain the restored image and unknown point spread function. The proposed approach is tested on three standard images and then compared with the previous methods using standard metrics. Real Passive Millimeter Wave (PMMW) images are also used to obtain the sharp deblurred images. Simulation results show that the proposed method can improve the quality of the restored image.

Multimodal Magnetic Resonance Imaging (MRI) is an imaging technique widely used in the diagnosis and treatment planning of patients. Lesion segmentation of brain MRI is one of the most important image analysis task in medical imaging. In this paper, a new method for the supervised segmentation of the lesion in brain MRI using Grammatical Bee Colony (GBC) is proposed. The segmentation process is adversely affected by the presence of noises and intensity inhomogeneities in the Magnetic Resonance (MR) images. Therefore, noises are removed from the images and intensity inhomogeneities are corrected in the pre-processing steps. A set of stationary wavelet features are extracted from the co-registered $T$1-weighted ($T1$-$W$), $T$2-weighted ($T2$-$W$) and Fluid–Attenuated Inversion Recovery (FLAIR) images after skull stripping. A classifier is evolved using the GBC to classify the tissues as healthy tissues or lesions. The GBC classifier is trained with extracted features. The trained classifier is used to segment the test Magnetic Resonance (MR) image into healthy tissues or lesion regions. Finally, the connected component labeling algorithm is used to extract the lesions from the segmented images in the post-processing step. Effectiveness of the proposed method is tested by identifying the brain lesions from a set of MR images.

An asymmetric architecture and energy-efficient capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) are proposed. The novel architecture achieves 81.25% reduction in capacitor area over the convention SAR. With the third reference voltage VCM and split-MSB switching procedure, the proposed switching scheme achieves 99.01% less switching energy over the convention SAR. Besides the significant energy saving, this asymmetric capacitor architecture also obtains a good performance in nonlinearity simulation. Based on the Matlab simulation for capacitor mismatch, the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.166LSB and 0.122LSB, respectively.

As the most popular nonlinear denoise technique, the median filter has attracted significant attention in recent years. In this paper, a novel adaptive median filter is presented to remove random-valued impulse noise in images, named Adaptive Partition-Cluster-Based Median (APCM) Filter. Based on the partition cluster idea, the noise detector classifies pixels into different groups and identifies the noisy pixels in different regions adaptively without iterations. According to the results of noise detection, an improved adaptive decision-based filter is presented to restore the pixels which are corrupted by random-valued impulse noise. The proposed filter technique is open to any impulse noise. Extensive simulation results demonstrate that the proposed method substantially outperforms other state-of-the-arts impulse noise filter techniques both visually and in terms of objective quality measures. Furthermore, the proposed method is much friendly to the hardware parallel implementation of image processing because of its low computation complexity and simple realizable structure.

A quasi-floating gate (QFG) “super-follower” is presented. The high resistance used by the QFG transistor is constructed by two diodes connected back-to-back, leading to a simple-, temperature-stable- and small-area solution. Expressions for the behavior of the follower are introduced and verified by circuit simulations in LTSPICE using 0.5$\mu$m CMOS process models, which show an improved performance of the proposed circuit with respect to the original super-follower. To prove the principle, a test cell was fabricated in the same 0.5$\mu$m CMOS technology and characterized. Measurement results show a gain-bandwidth product of 10MHz and power consumption of 120$\mu$W with a 1.5V single supply.

This paper describes three novel techniques such as drain gating PMOS transistor (DGPT), drain gating NMOS transistor (DGNT) and drain gating NMOS–PMOS transistor (DGNPT) for mitigation of leakage power, which are proposed to be used for low-power (LP) applications. The proposed techniques have leakage controlling sleep transistor inserted with sleep signal between pull-up and pull-down networks for reducing the leakage power. Simulation results are derived by HSPICE tool with PTM model for FinFET process fabrication at 32nm technology node at 25${}^{\circ }$C and 110${}^{\circ }$C temperatures. The proposed techniques are applied on standard and benchmark circuits, then these circuits are implemented on FinFET technology in short-gate (SG) and LP modes at 10MHz frequency. Simulation results show that the maximum reduction in leakage power by the proposed technique DGPT for two-input NAND gate is 99.34% in SG mode and in LP mode it is 99.83% at 25${}^{\circ }$C. DGNT technique gives the maximum saving in leakage power consumption of 97.17% in SG mode and in LP mode a maximum saving of 95.10% at 25${}^{\circ }$C is achieved. Similarly, DGNPT saves 99.34% in SG mode and in LP mode it saves 99.90% leakage power at 25${}^{\circ }$C with respect to conventional gates. The proposed techniques are also applied on different benchmark circuits and the results are validated. As an application of the proposed techniques, NAND gate is modified accordingly and it is used in 1-bit and 2-bit full-adder circuits.

The paper presents a new second-order single input multiple output (SIMO) type current mode (CM) universal filter. The proposed circuit uses two dual-X second generation multi-output current conveyors (DX-MOCCII), two grounded capacitors and three grounded resistors. The circuit configuration realizes low-pass filter (LPF), high-pass filter (HPF), band-pass filter (BPF), notch filter (NF) and all-pass filter (APF) responses simultaneously at different output terminals. The new circuit enjoys the features of low input impedance and high output impedance, which is desirable and useful for cascadability in CM circuits. For realizing the universal filter responses, the proposed circuit configuration does not require matching constraint of passive components and both active and passive sensitivities are found low. In addition, the extension of the proposed circuit as a resistorless universal filter has also been presented. As an application of the proposed filter, inverting band pass output is connected to a negative unity gain current follower in a close loop to design voltage and CM multiphase sinusoidal oscillators (MSOs). Comparison of the proposed configuration with available literature is given. The PSPICE simulation of the filter and its application as MSO are performed to verify the agreement with the theoretical proposition.

Hardware prefetching has always been a crucial mechanism to improve processor performance. However, an efficient prefetch operation requires a guarantee of high prefetch accuracy; otherwise, it may degrade system performance. Prior studies propose an adaptive priority controlling method to make better use of prefetch accesses, which improves performance in two-level cache systems. However, this method does not perform well in a more complex memory hierarchy, such as a three-level cache system. Thus, it is still necessary to explore the efficiency of prefetch, in particular, in complex hierarchical memory systems.

In this paper, we propose a composite hierarchy-aware method called CHAM, which works at the middle level cache (MLC). By using prefetch accuracy as an evaluation criterion, CHAM improves the efficiency of prefetch accesses based on (1) a dynamic adaptive prefetch control mechanism to schedule the priority and data transfer of prefetch accesses across the cache hierarchical levels in the runtime and (2) a prefetch efficiency-oriented hybrid cache replacement policy to select the most suitable policy. To demonstrate its effectiveness, we have performed extensive experiments on 28 benchmarks from SPEC CPU2006 and two benchmarks from BioBench. Compared with a similar adaptive method, CHAM improves the MLC demand hit rate by 9.2% and an improvement of 1.4% in system performance on average in a single-core system. On a 4-core system, CHAM improves the demand hit rate by 33.06% and improves system performance by 10.1% on average.

Despite its important existing challenges, quantum-dot cellular automata (QCA) is one of the promising replacement candidates of the traditional VLSI technology. Practical implementation issues such as fault tolerance and lack of customized CAD tools and algorithms for automatic synthesis of large complex systems are some important instances of QCA circuit design challenges. Currently, most of the research papers focus only on development of individually efficient QCA gates and circuits in terms of only their physical properties such as area and delay. However, throughout this paper, it is demonstrated that these compressed and fast individual QCA gates and circuits cause serious concerns when they are exploited as building blocks in modular design of higher level complex circuits. Some simple but effective design rules are then emphasized to solve this problem by preserving the “modular design efficiency” of the developed underlying QCA gates and circuits. As a case study, two new instances of fault-tolerant QCA XOR gates are introduced which are designed by simultaneously considering both area/delay and modular design efficiency rules. A wide range of numerical experiments are provided throughout the paper to prove the priority of the proposed gates with respect to eight other samples of the most efficient existing XOR structures, when exploiting them to build more complex circuits such as adders and error detection/correction circuits.

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180nm CMOS process and occupies a small area of 0.048mm² excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of $\pm$1.5${}^{\circ }$C from $-$45${}^{\circ }$C to 85${}^{\circ }$C under a supply voltage of 1.4–2.4V showing a worst-case supply sensitivity of 0.5${}^{\circ }$C/V. The sensor maintains a high conversion rate of 45KS/s with a fine resolution of 0.25${}^{\circ }$C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8V, the maximum energy consumption per conversion is only 7.8nJ at $-$45${}^{\circ }$C.