Research PaperNo Access

A Low-Power Low-Distortion 20-GS/s Flash Analog-to-Digital Converter for Coherent Optical Receiver in 0.13- $μ$ m SiGe BiCMOS

Jiquan Li

Institute of RF and OE-ICs, Southeast University, Nanjing, Jiangsu 210096, P. R. China

E-mail Address: 230159353@seu.edu.cn

Corresponding author.

Search for more papers by this author

Yingmei Chen

Institute of RF and OE-ICs, Southeast University, Nanjing, Jiangsu 210096, P. R. China

E-mail Address: njcym@seu.edu.cn

Search for more papers by this author

Pan Tang

Institute of RF and OE-ICs, Southeast University, Nanjing, Jiangsu 210096, P. R. China

Search for more papers by this author

Zhen Zhang

Institute of RF and OE-ICs, Southeast University, Nanjing, Jiangsu 210096, P. R. China

Search for more papers by this author

Hui Wang

Institute of RF and OE-ICs, Southeast University, Nanjing, Jiangsu 210096, P. R. China

Search for more papers by this author

, and

Hao Huang

Hubei Key Lab of Ferro and Piezoelectric Materials and Devices, Faculty of Physics and Electronic Science, Hubei University, Wuhan, Hubei 430062, P. R. China

Search for more papers by this author

https://doi.org/10.1142/S0218126619501676Cited by:2 (Source: Crossref)

Abstract

High-speed, low-power analog-to-digital converter (ADC) is a critical element for 5-GBd, 20-Gb/s digital signal processing (DSP)-based coherent optical communication receiver. To satisfy high data transmission rate requirement of optical receiver, a single-core and open-loop flash ADC with a new proposed multiplexer-based encoder is presented in this paper. Compared with conventional encoder topology, the new proposed topology achieves the fastest encoding speed and lowest power consumption. The optimized distortion is achieved by utilizing a leakage current compensation technique and a local negative feedback method in switched-buffer track-and-hold amplifier (THA). Strict synchronization is obtained for clock signals by careful designing of layout in tree-based clock networks. Furthermore, a master–slave comparator incorporated with a preamplifier reduces signal-dependent kickback noise as well as offset voltage. By using master–slave comparators and proposed encoders, the sampling rate is up to 21.12GS/s. The 4-bit, 20-GS/s flash ADC is realized in 0.13- $μ$ m SiGe BiCMOS technology and it only occupies 1.05mm $\times$ 1.46mm chip area. With a power consumption of 1.831W from 4-V supply, the ADC achieves an effective number of bits (ENOB) of 2.5 at 15GS/s.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

References

1. J. Lee, J. Weiner and Y.-K. Chen, A 20-GS/s 5-b SiGe ADC for 40-Gb/s coherent optical links, IEEE Trans. Circuits Syst. I, Regul. Pap. 57 (2010) 2665–2674. Google Scholar
2. J. Lee, P. Roux, U.-V. Koc, T. Link, Y. Baeyens and Y.-K. Chen, A 5-b 10-GSample/s A/D converter for 10-Gb/s optical receivers, IEEE J. Solid-State Circuits 39 (2004) 1671–1679. Crossref, Web of Science, Google Scholar
3. K. Poulton et al., A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 $μ$ m CMOS, Proc. 2003 IEEE Int. Solid-State Circuits Conf. Digest of Technical Papers (2003), pp. 318—319. Google Scholar
4. P. Schvan et al., A 24GS/s 6b ADC in 90nm CMOS, Proc. 2008 IEEE Int. Solid-State Circuits Conf. Digest of Technical Papers (2008), pp. 544–545. Google Scholar
5. W. Cheng, W. Ali, M.-J. Choi, K. Liu, T. Tat, D. Devendorf, L. Linder and R. Stevens, A 3b 40GS/s ADC-DAC in 0.12 $μ$ m SiGe, Proc. 2004 IEEE Int. Solid-State Circuits Conf. (2004), pp. 262–263. Google Scholar
6. M. Hudlička, C. Lundström, D. A. Humphreys and I. Fatadin, BER estimation from EVM for QPSK and 16-QAM coherent optical systems, Proc. IEEE 6th Int. Conf. Photonics (2016), pp. 1–2. Google Scholar
7. D. E. Crivelli, M. R. Hueda and H. S. Carrer, Architecture of a single-chip 50 Gb/s DP-QPSK/BPSK transceiver with electronic dispersion compensation for coherent optical channels, IEEE Trans. Circuits Syst. 61 (2014) 1016–1017. Google Scholar
8. D. Crivelli et al., A 40nm CMOS single-chip 50 Gb/s DP-QPSK/BPSK transceiver with electronic dispersion compensation for coherent optical channels, Proc. IEEE Int. Solid-State Circuits Conf. (2012), pp. 328–329. Google Scholar
9. P. Vorenkamp and J. Verdaasdonk, Fully bipolar, 120-Msample/s 10-b track-and-hold circuit, IEEE J. Solid-State Circuits 27 (1992) 988–990. Crossref, Web of Science, Google Scholar
10. E. Sall and and M. Vesterbacka, A multiplexer based decoder for flash analog-to-digital converters, Proc. IEEE Region 10 Conf. (TENCON) (2004), pp. 250–253. Crossref, Google Scholar
11. S. Shahramian, S. Voinigescu and A. Carusone, A 35-GS/s, 4-bit flash ADC with active data and clock distribution trees, IEEE J. Solid-State Circuits 44 (2009) 1709–1720. Crossref, Web of Science, Google Scholar
12. S. Sheikhaei, S. Mirabbasi and A. Ivanov, An encoder for 5 GS/s 4-bit flash ADC in 0.18 $μ$ m CMOS, Proc. Canadian Conf. Electrical and Computer Engineering (2005). Google Scholar
13. G. Roberts, F. Taenzler and M. Burns, An Introduction to Mixed-Signal IC Test and Measurement (Oxford University Press, Oxford, 2012). Google Scholar