Journal of Circuits, Systems and Computers

In this paper, an innovative approach to achieve broadband linear power amplifier (PA) with a continuous broadband is presented. The proposed method mainly depends on the theory of control of intermodulation products and harmonics. This method results in a continuous sweet spots over a wide bandwidth. Based on the continuous sweet spots, a suboptimal solution is derived for improving the efficiency and linearity of broadband PAs. To verify the effectiveness of this method, one broadband PA operating over 4.5–5.5GHz is developed and measured, it indicates that the peak output power of the PA is 35–57dBm for a small signal input with a gain of 12dB, and the peak drain efficiency (DE) of the PA is larger than 57% over the whole working band. However, when the PA is stimulated by a 5MHz two-tone signal input, we observe that the DE keeps above 38% under the condition of the measured third-order intermodulation distortion (IMD3) is not larger than $-30$dBc.

The classification of electroencephalogram (EEG) signals is a key technique of brain–computer interface (BCI) system. In view of the complexity of EEG signals and the low accuracy in EEG signals recognition, a motor imagery EEG signals classification method with multi-domain fusion based on Dempster–Shafer (D-S) evidence theory is presented in this paper. Firstly, time domain statistics (TDS), autoregressive (AR) model and discrete wavelet transform (DWT) are used to extract features from EEG signals, respectively, and three probabilistic output support vector machine (SVM) classification models are trained based on these three feature sets. Secondly, using the output of each SVM, we construct basic probability assignment (BPA) function and get fusion BPA through D-S evidence theory. Finally, determining the class of test samples based on decision rules. Four databases from BCI competition are employed to evaluate the proposed approach, and the highest classification accuracy reaches 92.83%. Results show that this method acquires higher accuracy and has strong individual adaptability.

We consider the problem of two-dimensional (2D) direction of arrival (DOA) estimation for planar array, and propose a successive propagator method (PM)-based algorithm. The rotational invariance property of the propagator matrix is exploited to obtain the initial angle estimations, while the accurate estimates can be achieved through successive one-dimensional and local spectrum-peak searches. The proposed algorithm can obtain automatically paired 2D-DOA estimations, and it requires no eigenvalue decomposition of the covariance matrix of received data, which remarkably reduces the computational cost compared with traditional 2D-PM algorithm. In addition, the DOA estimation performance of the proposed algorithm is better than estimation of signal parameters via rotational invariance technique (ESPRIT) algorithm and PM algorithm, and is close to 2D-PM algorithm which requires 2D spectrum-peak search. Numerical simulations demonstrate the effectiveness and improvement of the proposed algorithm.

A 36-kHz frequency locked on-chip oscillator is proposed, the proportional-to-absolute temperature (PTAT) current and voltage generator is presented to eliminate conventional temperature-compensated resistors. The resistorless approach reduces the process variation of frequency and the chip area. The oscillator is fabricated in 0.18-$\mu$m standard CMOS process with an active area of 0.072mm². The temperature coefficient of frequency is 48ppm/^∘C at best and 82.5ppm/^∘C on average over $-40^{}$–70^∘C and the frequency spread is 1.43% ($\sigma$/$\mu )$ without calibration. The supply voltage sensitivity is 1.8%/V in the range from 0.65V to 1V and the power consumption is 95nW under the supply voltage of 0.65V.

The growing complexity of digital designs makes it harder to discover inconsistency between system-level model (SLM) and register transfer-level (RTL) model. Equivalence checking is a promising solution to verify that the RTL description meets the requirements of the corresponding SLM description. However, the previously proposed formal equivalence checking approaches cannot handle designs if the mapping information is not given beforehand. Deep state sequences (DSSs)-based equivalence checking approach is the state-of-the-art equivalence checking approach based on Finite State Machines with Data Paths (FSMDs). But previously proposed DSS-based equivalence checking approach compared all the path-pairs blindly without pre-given mapping information, which wasted most verification efforts on useless comparisons. This paper proposes a novel DSS-based equivalence checking approach which can handle designs without pre-given mapping information and improve verification efficiency. Simulation technique is first used in our approach to generate mapping information of paths between SLM and RTL. With the generated mapping information, our approach can handle designs without pre-given mapping information. Only the generated corresponding path-pairs need to be compared by symbolic simulation, which improves the verification efficiency without blind comparisons. The experimental results show that the proposed approach can handle designs without pre-given mapping information and improve the efficiency of equivalence checking.

This paper explains the hidden positive feedback in a two-stage fully differential amplifier through external feedback resistors and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascade branches has been explained intuitively, with reference to previous literature. To avoid the latch-up problem, irrespective of the transistor bias currents, a novel hysteresis-based start-up circuit is proposed. An 87dB, 250MHz unity gain bandwidth amplifier has been developed in 65nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126$\mu$A from a 1.2V supply and occupies the 2184$\mu$m² area.

In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–$3.82\times$ higher compared to different existing techniques in FinFET SG mode and is 1.42–$3.29\times$ higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to $7.44\times$ higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.

A charge-controlled memristor emulator circuit based on one kind of active device [operational transconductance amplifier (OTA)] using CMOS technology is introduced in this paper. The proposed circuit can be configured in both incremental and decremental types by using a simple switch. The memristor behavior can be electronically tuned by adjusting the transconductance of the OTAs. By changing the value of the capacitor, the pinched hysteresis loop observed in the current versus voltage plane can be held at higher frequencies. The proposed emulator circuit functions well up to 500 kHz. The experiment has been performed using commercially available OTA ICs (CA3080). The experimental demonstration has been carried out for 10, 20 and 120kHz. A simple high-pass filter is explained in both configurations to demonstrate the functionality of the proposed memristor emulator. The proposed circuit has been simulated in PSPICE using 0.5-$\mu$m CMOS parameter. The simulated and experimental results validate the theoretical proposition.

High-speed, low-power analog-to-digital converter (ADC) is a critical element for 5-GBd, 20-Gb/s digital signal processing (DSP)-based coherent optical communication receiver. To satisfy high data transmission rate requirement of optical receiver, a single-core and open-loop flash ADC with a new proposed multiplexer-based encoder is presented in this paper. Compared with conventional encoder topology, the new proposed topology achieves the fastest encoding speed and lowest power consumption. The optimized distortion is achieved by utilizing a leakage current compensation technique and a local negative feedback method in switched-buffer track-and-hold amplifier (THA). Strict synchronization is obtained for clock signals by careful designing of layout in tree-based clock networks. Furthermore, a master–slave comparator incorporated with a preamplifier reduces signal-dependent kickback noise as well as offset voltage. By using master–slave comparators and proposed encoders, the sampling rate is up to 21.12GS/s. The 4-bit, 20-GS/s flash ADC is realized in 0.13-$\mu$m SiGe BiCMOS technology and it only occupies 1.05mm$\times$1.46mm chip area. With a power consumption of 1.831W from 4-V supply, the ADC achieves an effective number of bits (ENOB) of 2.5 at 15GS/s.

Emerging switched-mode power supplies incorporated applications demand reliable, less volume and high efficient dc–dc converters. The persistent usage of the dc–dc converters in various applications makes their reliability a significant concern. Hence, this paper deals with a family of non-isolated high gain integrated dc–dc converter topologies derived from a quadratic converter. The reliability analysis is carried out using electronic equipment reliability handbook, MIL-HDBK-217F. For the first time, reliability prediction is done based on the working environment of the power electronic equipments. We developed the reliability prediction for the converters used in the lighting application such as automotive headlamp and aircraft landing lights. The mean time to failure for both the environment is calculated. The reliability comparison is carried out for the proposed topologies and the most reliable converter is chosen. Also, all the converter topologies are simulated using nL5 simulator to confirm their theoretical results. Finally, a laboratory prototype for 40 W with input voltage of 12 V is implemented for the most reliable topology to validate the steady-state analysis.

A broadband (0.8–5GHz) CMOS current-mode direct-conversion receiver has been integrated in a 0.18-$\mu$m CMOS process. The proposed receiver front-end features a broadband active-balun low-noise transconductance amplifier (LNTA) driving a current-mode passive mixer terminated by a low-input-impedance transimpedance amplifier (TIA). The receiver chain has improved robustness to out-of-band interference, conversion gain and outstanding linearity. With the technique of noise and distortion cancellation which performs a better input impedance matching, we employ a broadband common-gate–common-source (CG–CS) LNTA and a current mirror to improve both gain and noise figure (NF) performance. Compared to the 50% duty-cycle switching stage, the 25% duty-cycle I–Q switching stage is implemented by using serial switches driven by 50% quadrature local oscillator (LO) signals separately, which improves the down-conversion gain by 3dB and lowers the noise figure. The transimpedance amplifier employs the $g_m$-boosting technique to realize low input impedance and high transimpedance gain. The core circuit (RF and baseband signal path) consumes 26mW, and the prototype receiver achieves approximately 33–34.5-dB conversion gain, 8.1–9.35-dB NF and 7.5–9.8-dBm IIP3 from 0.8GHz to 5GHz.

This paper introduces a methodology for implementing multi-band Doherty power amplifiers. Traditionally, a 90^∘ impedance inverter line is required in Doherty architecture. In this contribution, a generalized impedance inverter line is utilized to construct multi-band Doherty power amplifiers. A tri-band Doherty power amplifier operating at 1.15, 1.85 and 2.55GHz is designed to validate the proposed method. Measurement results show the fabricated Doherty power amplifier achieves 6dB output back-off drain efficiencies of 62.3%, 49.3% and 50.5% at 1.15, 1.85 and 2.55GHz, respectively. The peaking output power of the fabricated tri-band Doherty power amplifier is 43.2, 43.7 and 43.8dBm with drain efficiencies of 64.5%, 62.2% and 64.5% at three working frequency points, respectively. Furthermore, when the designed Doherty power amplifier is driven by a 20MHz wideband LTE signal with peak-to-average-power ratio of 6.4dB, adjacent channel power ratios of $-$29.4 and $-$57.1dBc are achieved before and after digital pre-distortion at 1.85GHz.

Power dissipation has been the prime concern for CMOS circuits. Approximate computing is a potential solution for addressing this concern as it reduces power consumption resulting in improved performance in terms of power–delay product (PDP). Decrease of power consumption in approximate computing is achieved by approximating the demand of accuracy as per the error tolerance of the system. This paper presents a new approach for designing approximate adder by introducing inexactness in the existing logic gate(s). Approximated logic gates provide flexibility in designing low power error-resilient systems depending on the error tolerance of the applications such as image processing and data mining. The proposed approximate adder (PAA) has higher accuracy than existing approximate adders with normalized mean error distance of 0.123 and 0.1256 for 16-bit and 32-bit adder, respectively, and lower PDP of 1.924E$-$18J for 16-bit adder and 5.808E$-$18J for 32-bit adder. The PAA also performs better than some of the recent approximate adders reported in literature in terms of layout area and delay. Performance of PAA has also been evaluated with an image processing application.

In this paper, an 8-bit ultra-low-power, low-voltage current steering digital-to-analog converter (DAC) is presented. The proposed DAC employs a new segmented structure that results in low integral nonlinearity (INL) and high spurious-free dynamic range (SFDR). Moreover, this DAC utilizes a low-voltage current cell. The low-voltage characteristic of the current cell is achieved by connecting the body of MOSFET switches to their sources. Utilizing a low supply voltage along with a low bias current in the current cells results in about 623.81-$\mu$W power consumption in 140-MS/s sample rate, which is very small compared to previous reports. The post-layout simulation results in 180-nm CMOS technology and $V_{DD}=0.9$-V supply voltage with the sample rate of 140MS/s show SFDR $>$ 64.37dB in the Nyquist range. The differential nonlinearity (DNL) and INL of the presented DAC are 0.1254 LSB and 0.1491 LSB, respectively.

The paper presents the development of an algorithm to obtain stable allpass filter, which acts as a group delay equalizer, with the aim to equalize group delay of the polynomial IIR filter in a maximal flat sense. The proposed method relies on a set of nonlinear equations, derived directly from the flatness conditions of the group delay response at the origin in the $z$-plane, with the order to obtain the unknown values of the allpass filter coefficients. The algorithm implemented in the MATLAB platform returns the coefficients of allpass filter. In the given example, first we construct a minimum phase polynomial IIR digital filter with a maximally flat magnitude at origin, next we augment the system with cascade connection of nonminimum allpass digital filter with order to equalize the group delay response of the whole filter in a maximally flat sense.

In this paper, the study of a Ka-band GaAs HBT VCO is reported with particular emphasis on achieving low-phase noise while using direct coupled varactor. A push–push cross-coupled VCO configuration is employed to achieve high oscillation frequency and low-phase noise. The measured oscillation bandwidth spans from 30.2 to 28.6GHz with a tuning range of 1.6GHz, while the phase noise at 1MHz of frequency offset from the carrier at 29.3GHz is $-111.5$dBc/Hz. The VCO consumes 28.2mW from 3V supply and occupies an area of $0.82\mathrm{\text{mm}}\times 0.62$mm. The FOM of the VCO achieves $-186.3$dBc/Hz.

High-brightness light-emitting diode (LED) lamps have attracted much attention because of their high efficiency, simple structure, energy conservation and environmental protection aspects, and long lifetime. Thus, an LED driver must have a long lifespan, high density, and compact space. However, conventional LED power supplies use an electrolytic capacitor as the storage capacitor in the holdup time, which has a short lifespan and occupies large space. In this paper, a novel synchronous current-doubler rectifier (SCDR) method is proposed as an LED driver. The reasonably designed circuit is used to control the output voltage ripple in the normal range without adding a complicated control circuit. The proposed topology is designed using few components, has no electrolytic capacitor, and has a low cost for high-output current LED driver applications. Circuit operating principles and detailed theoretical analysis are provided in this paper. A 200-W prototype has been established and tested, and the experimental results are presented to highlight the merits of the proposed circuit.

Informative images endure from poor contrast and noise during image acquisition. Significant information retrieval necessitates image contrast enhancement and removal of noise as a prerequisite before any further processing can be done. Dominant applications with low contrast images affected by speckle noise are medical ultrasound images. The objective of this work is to improve the effectiveness of the preprocessing stage in medical ultrasound images by enhancing the image while retaining its structural characteristics. For image enhancement, this work proposes to develop an automatic contrast enhancement technique using cumulative histogram equalization and gamma correction based on the image. For noise removal, this work proposes an algorithm Gamma Correction with Exponentially Adaptive Threshold (GCEAT) which suggests the use of GC for contrast enhancement along with a new wavelet-based adaptive soft thresholding technique for noise removal. The proposed GCEAT-based image de-noising is validated with other enhancement and noise removal techniques. Experimental results with low contrast synthetic and actual ultrasound images show that the suggested proposed system performs better than existing contrast enhancement techniques. Encouraging results were obtained with medical ultrasound images in terms of Peak-Signal to Noise Ratio (PSNR), Mean Square Error (MSE), Structural Similarity Index Measure (SSIM) and Average Intensity (AI).

The time-triggered CAN (TTCAN) protocol has been widely used in the automotive industry to fulfil the safety and real-time requirements of the application. As an extension of the standard CAN protocol, the TTCAN protocol aims to guarantee a safe and deterministic communication by introducing time-triggered messages with respect to a global synchronized time, which are scheduled in independent transmission windows within the system matrix. However, the new features bring more difficulties in designing and verifying the reliable applications in the TTCAN network. In this paper, we first present a formal probabilistic model of the TTCAN protocol with a consideration of its novel features. A TTCAN system consisting of three parts, i.e., a system matrix, an arbitration and some nodes, is modeled as discrete Markov chains model. Furthermore, five probabilistic properties are described and verified in the probabilistic model checker tool PRISM. Our work gives a quantitative analysis method for the given requirements, which facilitates the designers to a formal understanding of TTCAN protocol.