Journal of Circuits, Systems and Computers

The state-of-the-art development and subsequent miniaturization of technologies in e-systems such as computers and digital communication systems have led to densely and compactly placement of devices and interconnects in ICs. The incessant advancements of technologies have necessitated a rapid increase in operating frequencies. At nanometer dimensions and advanced technology nodes, the performance of the overall VLSI system is critically dominated by on-chip interconnects. Interconnects perpetuate several nonideal effects such as signal delay, power dissipation and cross-talk that limit the overall system performance. Owing to graving effect of interconnects on the performance parameters in ICs, research into interconnects has become meticulously very active in recent years, and concurrently much progress has been made. In this review paper, a literature review and contemporary advancements on conventional aluminum, copper and subsequent next generation graphene interconnects have been systematically presented.

In outdoor scenes, haze limits the visibility of images, and degrades people’s judgement of the objects. In this paper, based on an assumption of human visual perception in frequency domain, a novel image haze removal filtering is proposed. Combining this assumption with the theory of frequency domain filtering, we first estimate the cut-off frequency to divide the frequency domain of the hazy image into three components — low-frequency domain, intermediate-frequency domain and high-frequency domain. Then, by introducing the weighting factors, the three components are recombined together. After the theoretical deduction of frequency domain, the establishment of the actual model and adjusting the cut-off frequency and weighting factors, we finally acquire a global and adaptive filtering. This filtering can restore the details and the contours of the images, which have less noise, and improve the visibility of the objects in hazy images. Moreover, our method is simple in structure and strongly applicable, and rarely affected by parameters. Our algorithm is stable and performs well in heavy fog and the scene changes.

This paper presents resistorless realization of inverse filters using voltage differencing transconductance amplifier (VDTA). First, four topologies are proposed which provide inverse low-pass, high-pass, band-pass, and band-reject responses. Subsequently, a unified inverse filter is also derived by incorporating two switches in the combination of proposed inverse low-pass and inverse band-pass topologies. This topology is capable of providing inverse low-pass, inverse high-pass, inverse band-pass, and inverse band-reject responses by appropriate switch settings. The proposed inverse filter structures are electronically tunable and use only grounded capacitors. The behavior of the proposed filters is also investigated for nonidealities. To verify the functionality of the proposed inverse filter circuits, SPICE simulation is carried out using 0.18-$\mu$m CMOS technology parameters from TSMC. The effect of deviation in the active and passive component values on angular frequency is tested through Monte Carlo simulation.

Miniaturization and the continued scaling of CMOS technology leads to the high-power dissipation and ever-increasing power densities. One of the major challenges for the designer at all design levels is the temperature management, particularly the local hot spots along with power dissipation. In this work, the controller circuits which are implemented as Finite State Machines (FSMs) are considered for their thermal-aware and power-aware realization. Using Genetic Algorithm (GA), both encoding and bipartitioning of the FSM circuit are implemented to get two subFSMs such that at a particular instant of time, one subFSM is active at a time, whereas the other one is power-gated. Again, thermal-aware realization (in terms of power-density) of this power-gated FSM is done. Therefore, the work concerns with the thermal-aware encoding and partitioning of FSM for its power-gated realization. Average temperature saving obtained in this approach for a set of benchmark circuits over previous works is more than 16%. After getting the final partitioned circuit which is optimized in terms of Area and power-density, thermal analysis of the sunFSMs is performed to get the absolute temperature. As thermal-aware design may increase the area, a suitable area-temperature trade-off is also presented in this paper.

With the continued scaling of the CMOS device, the exponential increase in power density has strikingly elevated the temperature of on-chip systems. In this paper, the problem of allocating and scheduling frame-based real-time applications is addressed to multiprocessors to minimize the makespan under the thermal and timing constraints. The proposed algorithms consist of offline and online components. The offline component assigns the applications accepted at static time to processors in a way that the finish time of processors are balanced. The online component firstly selects the processor with the highest allocation probability for each application accepted at runtime. The allocation probability is calculated by taking the processor workload and temperature profiles into consideration. The higher allocation probability of a processor shows the better performance with respect to makespan and temperature can be achieved by executing the application on this processor. Then, the operating frequencies of applications are determined by making the most of slack in order to reduce the peak temperature under the timing constraint. Extensive simulations were performed to validate the effectiveness of the proposed approach. Experimental results have shown that the static makespan of the proposed scheme is very close to the optimal schedule length within a small margin varying from 0.118s to 0.249s, and the dynamic makespan of the proposed scheme can be adapted to satisfy varying system design constraints. The peak temperature of the proposed algorithms can be up to $13.7\%$ lower than that of the benchmarking schemes.

The aging effect induced by negative bias temperature instability (NBTI) is a universal issue existing in electronic equipments. NBTI aging effect can increase the path delay of network-on-chip (NoC) device, resulting in the decreased frequency of processor core and in turn its performance degradation. Under this circumstance, aging-aware task scheduling becomes a complex and challenging problem in advanced multicore systems. This paper presents an aging-aware scheduling method that incorporates NBTI aging effect into the task scheduling framework for mesh-based NoCs. The proposed method relies on a NBTI aging model to evaluate the degradation of core’s operating frequency to establish the task scheduling model under aging effect. Taking into account core performance degradation and the communication overheads among cores, we develop a meta-heuristic scheduling strategy based on particle swarm optimization algorithm to minimize the total execution time of all tasks. Experimental results show that the schedule obtained by the aging-aware algorithm has shorter completion time and higher throughput compared with the nonaging-aware case. On average, the makespan can be reduced by 13.55% and the throughput can be increased by 21.73% for a variety of benchmark applications.

The query probability of a location which the user utilizes to request location-based service (LBS) can be used as background knowledge to infer the real location, and then the adversary may invade the privacy of this user. In order to cope with this type of attack, several algorithms had provided query probability anonymity for location privacy protection. However, these algorithms are all efficient just for snapshot query, and simply applying them in the continuous query may bring hazards. Especially that, continuous anonymous locations which provide query probability anonymity in continuous anonymity are incapable of being linked into anonymous trajectories, and then the adversary can identify the real trajectory as well as the real location of each query. In this paper, the query probability anonymity and anonymous locations linkable are considered simultaneously, then based on the Markov prediction, we provide an anonymous location prediction scheme. This scheme can cope with the shortage of the existing algorithms of query probability anonymity in continuous anonymity locations difficult to be linked, and provide query probability anonymity service for the whole process of continuous query, so this scheme can be used to resist the attack of both of statistical attack as well as the infer attack of the linkable. At last, in order to demonstrate the capability of privacy protection in continuous query and the efficiency of algorithm execution, this paper utilizes the security analysis and experimental evaluation to further confirm the performance, and then the process of mathematical proof as well as experimental results are shown.

To provide high vertical interconnection density between device tiers, Through Silicon Via (TSV) offers a promising solution in 3D caches. It reduces the length of global interconnection and ensures high speed cache memory access. Maintaining coherency of shared data in such caches is, however, very crucial and, therefore, demands that the reliability and accuracy of TSVs as well as the cache coherence controller (CC) are to be ensured. In the current work, we propose an elegant test solution for at-speed detection of stuck-at-faults in TSVs (offline test) as well as verification for the functioning of CC (online test). The proposed test structure is designed around the modular and cascadable structure of Cellular Automata (CA) to achieve a cost-effective realization of test and coherence verification in 3D caches with high degree of scalability. It ensures correct decisions in more than 71% cases even if the test hardware is subjected to single stuck-at-fault.

This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of $5M+4S+2D$ and $5M+4S+1D$ for general and special cases of BECs, respectively, where $M,S$ and $D$ denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields ${𝔽}_{2^{163}}$ and ${𝔽}_{2^{233}}$ are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.

Speckle noise in ultrasound images is a major hindrance for the automation of segmentation, detection, classification and measurements of region of interest, to assist clinician for diagnosing pathologies. Speckle noise occurs due to constructive and destructive interference of the echo signals reflected from the target and has a granular appearance. Various techniques have been devised for speckle reduction. Most of these techniques are based on adaptive filters, wavelet transform and anisotropic diffusion filters. In this paper, a new speckle reduction technique based on the trilateral filter and local statistics of the image has been developed. The local speckle content of the image influences the trilateral filtering. The trilateral filter is a robust edge preserving filter which considers the similarity of neighboring regions in terms of adjacency, intensity and edge details. Hence, the new method preserves the finer details of the ultrasound images in the process of filtering speckle noise. The proposed technique is validated using synthetic, simulated and real-time clinical ultrasound images. Comparison of the proposed technique with the existing speckle removal algorithms in terms of quality metrics such as MSE, PSNR, UQI, SSI, FoM has been made and best results are obtained for the proposed technique.

Over the last 40 years, the design of $n$-dimensional hyperchaotic systems with a maximum number ($n-2$) of positive Lyapunov exponents has been an open problem for research. Nowadays it is not difficult to design $n$-dimensional hyperchaotic systems with less than ($n-2$) positive Lyapunov exponents, but it is still extremely difficult to design an $n$-dimensional hyperchaotic system with the maximum number ($n-2$) of positive Lyapunov exponents. This paper aims to resolve this challenging problem by developing a chaotification approach using average eigenvalue criteria. The approach consists of four steps: (i) a globally bounded controlled system is designed based on an asymptotically stable nominal system with a uniformly bounded controller; (ii) a closed-loop pole assignment technique is utilized to ensure that the numbers of eigenvalues with positive real parts of the controlled system be equal to ($n-1$) and ($n-2$), respectively, at two saddle-focus equilibrium points; (iii) the number of average eigenvalues with positive real parts is ensured to be equal to ($n-2$) for the controlled system over a given control period; (iv) the smallest value of the positive real parts of the average eigenvalues is ensured to be greater than a given threshold value. Finally, the paper is closed with some typical examples which illustrate the feasibility and performance of the proposed design methodology.

The characterization of interconnect delay metrics in terms of process variations is an important but complicated task for statistical timing analysis in today’s integrated circuits (ICs). This paper presents a stochastic delay characterization framework for multicoupled interconnects in the presence of process variation. The proposed method starts with deriving the stochastic nodal equations for the RLC network that models multicoupled interconnects. By employing polynomial chaos (PC) expansion, a nonsampling-based stochastic prediction method, we further represent the voltage responses of network nodes as a series of orthogonal polynomials of random variables. During the expansion procedure, we use an adaptive approximation algorithm to reduce the number of required sampling points. We then use a stochastic collocation method to estimate the coefficients in the PC expansion model. With the voltage response determined as an expression of a multi-dimensional polynomial of random variables, the stochastic properties of the delay of multicoupled interconnects can be predicted. The proposed method not only takes into account the strong correlations among process variations, but also extracts an explicit delay representation for multicoupled interconnects in terms of process variations. Experimental results demonstrate that the delay characteristics predicted by the proposed method match well with the results by the brute-force Monte-Carlo method. Moreover, a significant speedup over the Monte-Carlo method has been achieved by the proposed delay characterization framework.

In this work, novel swarm optimization algorithm based on the Artificial Bee Colony (ABC) algorithm called Enhanced Artificial Bee Colony (EABC) algorithm is proposed for the design and optimization of the analog CMOS circuits. The new search strategies adopted improve overall performance of the proposed algorithm. The performance of EABC algorithm is compared with other competitive algorithms such as ABC, GABC (G-best Artificial Bee Colony Algorithm) and MABC (Modified Artificial Bee Colony Algorithm) by designing three CMOS circuits; Two-stage operational amplifier, low-voltage bulk driven OTA and second generation low-voltage current conveyor in 0.13 $\mu$m and 0.09$\mu$m CMOS technologies. The obtained results clearly indicate that the performance of EABC algorithm is better than other mentioned algorithms and it can be an effective approach for the automatic design of the analog CMOS circuits.

This paper proposes a new and efficient hybrid approach combining two meta-heuristic methods for solving economic and emission dispatch problems. We used particle swarm optimization (PSO)-based gray wolf optimization to solve this problem. Additionally, the nonlinear control parameter is employed to balance the global search and local search ability of the algorithm and improve the convergence speed of the algorithm. At the same time, the idea of PSO is introduced, which utilizes the best value of the individual and the best value of the wolf pack to update the position information of each gray wolf. This method preserves the best position information of the individual and avoids the algorithm falling into a local optimum. The optimal power flow (OPF)-based CEED problem is formulated with the combination of fuel cost, fuel emission with penalty function, real power loss and voltage deviation. The proposed approach is implemented in MATLAB working platform and tested by IEEE 30 bus system with different test cases. Moreover, the CEED problem-solving performance of PSGWO algorithm is examined by 3-unit, 6-unit and 40-unit test systems. Then, the obtained results are compared with conventional methods to highlight the benefits of the proposed algorithm in reducing the fuel cost, fuel emission, voltage deviation and power losses, respectively. The experimental results show that the proposed approach provides accurate solutions for all types of objective solutions.

This paper presents a two-stage synchronous rectifier interface circuit for piezoelectric energy harvesting (PEH) system. The proposed rectifier includes a first-stage negative voltage converter, a second-stage adaptive on-resistance active diode, and combines a precise switch-on-time controlled P-SSHI circuit. The traditional active two-stage synchronous rectifier has lower current detection accuracy and hardly achieves high efficiency rectification over a wide input current range. An adaptive on-resistance active diode (AOR active diode) is proposed to replace the traditional active diode to achieve higher current zero-crossing detection accuracy, improve the input current range and the output power of the rectifier. The proposed diode allows the rectifier to maintain high rectification efficiency over a wider input current range. Further, a parallel synchronized switch harvesting on inductor (P-SSHI) with precise switch-on-time controlled circuit is proposed to achieve higher voltage flipping efficiency and improve the power extraction capability of the rectifier. By using the AOR active diode and the P-SSHI with precise switch-on-time controlled circuit, a good performance improvement has been achieved for the proposed interface circuit. The design is fabricated in an SMIC 0.35$\mu$m standard CMOS technology with a die size of $1.23\times 1.12$mm². The simulation results indicate that the proposed circuit achieves more than 80% power converting efficiency and its peak efficiency is 85%. The current zero-crossing detection accuracy of the proposed AOR active diode is less than 10$\mu$A. The proposed PEH interface circuit extracts up to 2.81 times more output power compared with a traditional rectifier. The voltage flipping efficiency of the P-SSHI circuit is up to 90%, which can effectively improve the power extraction capability of the rectifier. Moreover, the proposed circuit can be self-powered and cold started up.

The discovery of ultra-high-speed all-optical switches in the very recent past based on semiconductor optical amplifier (SOA) especially in the interferometric configuration is very pronouncing due to their features like high repetition rate, low power consumption, fast switching time, noise and jitter tolerance, being easily integrable and operationally versatile, thereby bringing a revolution in all-optical information processing systems. In this work, an all-optical computing tool namely SOA-based $2\times 2$ terahertz optical asymmetric demultiplexer (TOAD) is used because it can be employed to design more complex circuits and subsystems of enhanced combinational and sequential functionality. In this paper, (a) a switching network with its two switching actions and (b) an all-optical $8\times 8$ cross-bar network architecture, i.e., a multistage cube network for $N=8$ using TOAD-based $2\times 2$ optical cross-bar switch for discrete Fourier transform (DFT), are proposed. Numerical simulation of this work is done with OptiSystem v7.0 to evaluate the performance of the proposed circuit.

This paper presents a novel high-speed and highly energy-efficient double-tail dynamic comparator. In order to achieve high speed, a hybrid design style is adopted for pre-amplifier stage and a new design is proposed for latch stage, which enhances the speed and reduces the effect of kickback noise. The latch stage delay and energy efficiency of the proposed design are optimized with respect to the width of each transistor. To verify the outcomes, the proposed comparator is simulated using 45nm and 180nm CMOS process. Monte Carlo simulation is also done for each parameter. The 45nm result shows that the comparator has the total delay as low as 104.3ps and consumes only 0.288fJ of energy per conversion from a 0.8V supply. The mean value of input voltage error due to kickback noise is found as 306nV.

This paper presents a three-winding coupled inductor-based high-gain DC–DC converter fed transformerless dynamic voltage restorer (TDVR) to compensate the voltage sag, voltage swell and interruption in the single-phase power distribution network. The TDVR supported by the cascaded DC–DC boost converters offers high boosting gain. The cascaded connection of DC–DC converters reduces the efficiency due to the usage of more active and passive devices. The proposed PV-TDVR is designed to provide higher efficiency by reducing the number of power conversion stages with reduced numbers of active and passive components. The operating modes of the proposed PV-TDVR are presented in a comprehensive way. The MATrix LABoratory (MATLAB) simulation and 1-kV prototype model results are presented to analyze the performance of PV-TDVR in mitigating the voltage disturbances in the single-phase power distribution network.

With the rapid development of commercialized computation, the heterogeneous computing system (HCS) has evolved into a new method of service provisioning based on utility computing models, in which the users consume services and resources based on their quality of service requirements. In certain models using the pay-as-you-go concept, the users are charged for accessed services based on their usage. In addition, the commercialized HCS provider also assumes the responsibility to reduce the energy consumption to protect the environment. This paper considers a basic model known as directed acyclic graphs (DAG), which is designed for workflow applications, and investigates heuristics that allows the scheduling of various tasks of a workflow into the dynamic voltage and frequency scaling enabled HCS. The proposed approaches, which are Minimum-Cost-Up-to-Budget (MCUB) and Maximum-Cost-Down-to-Budget (MCDB), could not only satisfy budget constrains but could also optimize overall energy consumption. The approaches along with their variants are implemented and evaluated using four types of basic DAGs. From the experimental results, we conclude that MCDB outperforms MCUB in energy optimization and makespan criterion while meeting budget constraints faced by users.