Narrow Results

We present an overview of radiation effects in silicon-germanium heterojunction bipolar transistors (SiGe HBT). We begin by reviewing SiGe HBTs, and then examine the impact of ionizing radiation on both the dc and ac performance of SiGe HBTs, the circuit-level impact of radiation-induced changes in the transistors, followed by single-event phenomena in SiGe HBT circuits. While ionizing radiation degrades both the dc and ac properties of SiGe HBTs, this degradation is remarkably minor, and is far better than that observed in even radiation-hardened conventional Si BJT technologies. This fact is particularly significant given that no intentional radiation hardening is needed to ensure this level of both device-level and circuit-level tolerance (typically multi-Mrad TID). SEU effects are pronounced in SiGe HBT circuits, as expected, but circuit-level mitigation schemes will likely be suitable to ensure adequate tolerance for many orbital missions. SiGe HBT technology thus offers many interesting possibilities for space-borne electronic systems.

We present design considerations for high speed high swing differential modulator drivers in SiGeBiCMOS technology. Trade-offs between lumped and distributed designs, and linear and limiting amplifiers are examined. The design of a 6 V output modulator driver is discussed in detail. The driver features a unique bias generation and distribution circuit that enables low power-supply operation. Simulation results and measurements are given.

In this article is presented the new SON process, which key point lies in the transfer of the lattice continuity from a bulk Silicon substrate via a SiGe layer to the Silicon cap layer, both of these layers being obtained by epitaxy. The thin SiGe layer is next removed from underneath the Si cap in an isotropic plasma-assisted chemical dry-etching. The mono-crystalline Si cap layer resulting from this process lies on an air-gap, which gives the name (Silicon On Nothing) to the process. Depending on application, this air-gap may be refilled with a dielectric or with a gate material for double gate applications. In both cases, the thickness of the Si cap as well as that of the air-gap (filled by the dielectric for single gate applications) may be in the range of a few nanometers with a control in the range of the epitaxy process capability. In this article we present the SON process and its implementation to MOSFETs devices and circuits. This development effort converges towards an SON technological platform, allowing easy co-integration of SON and bulk transistors, Gate All Around or multi-gate devices.

Energy efficient hetero-junction tunneling transistors in a simple "cross-point" configuration that utilizes top gates are analyzed for use at extremely scaled sub-10 nm gate-lengths. The active tunneling region comprises of a vertical p++/n+ heterojunction (for example formed at the cross point of p++SiGe/n+Si), where modulation of the energy-bands in the gated n+Si region with a top-gate is used to control the degree of band overlap and tunneling distance and hence current. The sub-threshold swing characteristic of these devices is shown to be potentially highly immune to extreme downscaling to 6 nm gate length allowing for an intact and efficient switching behavior to be retained. The extreme scalability and ultra-low voltage operation could make such cross-point devices useful for alternative applications and architectures that require ultimate energy efficiency.

In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 10²⁰ cm⁻³. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO₂ as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.

We present a complete Monte Carlo simulation of the transport properties of a Si/SiGe quantum well. The scattering mechanisms, viz. intervalley phonons, acoustic phonons, interface roughness and impurity scattering (including resonant scattering), are considered in detail, and we derive analytic expressions for the scattering rates, in each case properly taking the quantized electron wave functions into account. The numerically obtained distribution function is used to discuss the influence of each scattering mechanism for different electric fields applied parallel to the interfaces and also different temperatures.

Since crystal structure dictates the resultant physical properties of materials, titled physical features of the P2₁ monoclinic SiGe semiconductors, which are still unclear, have been revealed by density functional theory (DFT). The electronic band gap value with 0.49eV was found to be in the order of previously published cubic and hexagonal closed-packed SiGe semiconductors. Surprisingly, P2₁ monoclinic SiGe has a room temperature Seebeck coefficient of 1500$\mu$V/K which is higher than the reported data of both cubic and hexagonal SiGe alloys. Further, the mechanically stable P2₁ monoclinic phase of the SiGe displays a brittle mechanical character with clear elastic anisotropy has also been deduced. The P2₁ monoclinic phase of the SiGe can be also considered a good high-dielectric material and beneficial for practical applications of IR or UV goals due to its high refractive index.

The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz Field Programmable Gate Arrays (FPGAs).^1,2 The integration of high-speed SiGe HBTs and low-power CMOS gives a significant speed advantage to SiGe FPGAs over CMOS FPGAs. In the past, high static power consumption discouraged the pursuit of bipolar FPGAs from being scaled up significantly. This paper details new ideas to reduce power in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to reduce circuitry and utilize a novel power management scheme to achieve a flexible trade-off between power consumption and circuit speed. In addition, new decoding logic is developed with shared address and data lines. A SiGe FPGA test chip based on the Xilinx 6200 architecture has been fabricated for demonstration.

A fully integrated push–push voltage controlled oscillator (VCO) working in K-band with a large tuning range and a low phase noise fabricated in a 0.18 μm SiGe BiCMOS technology is presented. Multi-coupled LC tanks are used to improve the tuning range, power consumption and phase noise. Digital tuning varactors are used to maintain a low VCO tuning sensitivity (K_VCO) and maximum frequency overlap. The VCO achieves a frequency tuning range (FTR) of 17% at 12 GHz, a phase noise of -106.62 dBc/Hz at 1 MHz offset and consumes 7 mW from 1.8 V supply.

High-speed, low-power analog-to-digital converter (ADC) is a critical element for 5-GBd, 20-Gb/s digital signal processing (DSP)-based coherent optical communication receiver. To satisfy high data transmission rate requirement of optical receiver, a single-core and open-loop flash ADC with a new proposed multiplexer-based encoder is presented in this paper. Compared with conventional encoder topology, the new proposed topology achieves the fastest encoding speed and lowest power consumption. The optimized distortion is achieved by utilizing a leakage current compensation technique and a local negative feedback method in switched-buffer track-and-hold amplifier (THA). Strict synchronization is obtained for clock signals by careful designing of layout in tree-based clock networks. Furthermore, a master–slave comparator incorporated with a preamplifier reduces signal-dependent kickback noise as well as offset voltage. By using master–slave comparators and proposed encoders, the sampling rate is up to 21.12GS/s. The 4-bit, 20-GS/s flash ADC is realized in 0.13-$\mu$m SiGe BiCMOS technology and it only occupies 1.05mm$\times$1.46mm chip area. With a power consumption of 1.831W from 4-V supply, the ADC achieves an effective number of bits (ENOB) of 2.5 at 15GS/s.

Experimental data are presented on variations of the in-plane lattice constant of Ge and Si films in the course of the MBE film growth on the silicon (100) surface. The in-plane lattice constant of the silicon film is shown to alter as the film grows; the changes reflect the process of relaxation of elastic strains that result from the misfit of the germanium and silicon lattice constants. Due to the presence of germanium islands, a considerably thicker silicon film is required to provide the strain relaxation. The dependence of distortion penetration depth to the silicon film on the effective germanium film thickness is obtained. TEM studies indicate the vertical ordering of the germanium island layers when the thickness of the Si layer in between Ge layers is not sufficient to provide the full strain relaxation.

Quantum optics and photonic quantum-information technologies require emitters that have good stability and brightness, coupled with fabrication scalability and on-chip integrability. Most quantized emitters are presently based on 1D and 3D sources. Recently, monolayer transition metal dichalcogenides (TMDCs) hosting spatially localized excitons with narrow linewidths have garnered great interest. Advantages such as large binding energies and long room-temperature lifetimes of intralayer excitons suggest that TMDCs are promising candidates for use in optical devices. Here, we propose an emitter based on a 2D WSe₂ semiconductor monolayer integrated with a periodic 3D Si-based wrinkled pattern. Carriers confined within the wrinkled pattern can be electrically and optically pumped, and funneled, to boost emission from the 2D WSe₂ layer. This in turn acts as a monochromated quantum light source for the Si or any Si-based quantum optic and photonic information technologies. The brightness of the emission is enhanced by a factor greater than 40 compared with monolayer WSe₂ on conventional flat SiGe. Moreover, these monolayer 2D/3D semiconductor composite heterostructures are fully scalable and promisingly efficient chip-integrated emitters.

In this article is presented the new SON process, which key point lies in the transfer of the lattice continuity from a bulk Silicon substrate via a SiGe layer to the Silicon cap layer, both of these layers being obtained by epitaxy. The thin SiGe layer is next removed from underneath the Si cap in an isotropic plasma-assisted chemical dry-etching. The mono-crystalline Si cap layer resulting from this process lies on an air-gap, which gives the name (Silicon On Nothing) to the process. Depending on application, this air-gap may be refilled with a dielectric or with a gate material for double gate applications. In both cases, the thickness of the Si cap as well as that of the air-gap (filled by the dielectric for single gate applications) may be in the range of a few nanometers with a control in the range of the epitaxy process capability. In this article we present the SON process and its implementation to MOSFETs devices and circuits. This development effort converges towards an SON technological platform, allowing easy co-integration of SON and bulk transistors, Gate All Around or multi-gate devices.

In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 10²⁰ cm⁻³. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760−825 °C. The results demonstrated that the thermal budget has to be within 780−800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO₂ as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.