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Design and Simulation of Multi-State D-Latch Circuit Using QDC-SWS FETs

A. Almalki

Department of Electrical and Computer Engineering, University of Connecticut, CT, USA

Department of Electrical Engineering, College of Engineering, Taif University, Saudi Arabia

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B. Saman

Department of Electrical and Computer Engineering, University of Connecticut, CT, USA

Department of Electrical Engineering, College of Engineering, Taif University, Saudi Arabia

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R. H. Gudlavalleti

Department of Electrical and Computer Engineering, University of Connecticut, CT, USA

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J. Chandy

Department of Electrical and Computer Engineering, University of Connecticut, CT, USA

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E. Heller

Synopsys Inc., Ossining, NY 10562, USA

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, and

F. C. Jain

Department of Electrical and Computer Engineering, University of Connecticut, CT, USA

E-mail Address: faquir.jain@uconn.edu

Corresponding author.

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https://doi.org/10.1142/S012915642350009XCited by:0 (Source: Crossref)

This article is part of the issue:

Special Issue on Nanotechnology in Electronics, Photonics, Biosensors, and Energy Systems
Guest Editors: F. Jain, C. Broadbridge, M. Gherasimova and H. Tang

Abstract

This paper presents a novel D-latch circuit using multi-state quantum dot channel (QDC) spatial wavefunction-switched (SWS) field-effect transistors (FET). The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in each channel. Spatial location is used to encode multiple logic states along with the carrier transport in mini-energy bands formed in GeO_x-Ge/ SiO_x-Si quantum dot superlattice (QDSL), and to obtain 8-states operation. The design is based on the 8-state inverter using QDC SWS-FETs in CMOS-X configuration. This could be a new paradigm for designing flip-flops and registering more complex sequential circuits. The proposed design leads to reduced propagation delay and a smaller Si footprint.

Keywords:

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