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Compared to multi-valued logic (MVL) with conventional 2-state FETs with a single threshold, MVL computing architectures, based on 4-state SWS (Spatial wavefunction switched) and QDG (quantum dot gate)-FETs having multiple thresholds, results in reduced device count, higher clock (CLK) speed, and lower power consumption. We have experimentally shown multi-state characteristics in SWS-FETs as well as QDG-FETs. This paper presents a novel QDG-SWS-FET that: (1) functions as a multi-bit FET for efficient low-power logic, (2) can be configured as a quantum dot (QD) nonvolatile random access memory (NVRAM), and (3) is suitable for in-memory MVL computing architecture that are compatible with sub-7nm technology nodes. A QDG-SWS-FET with the addition of a control gate dielectric layer functions as a NVRAM cell. Furthermore, it is shown that one single SWS-QD-NVRAM cell gives the functionality of a 1-bit NAND. We have developed circuit/device models and performed quantum simulations for novel multi-layer quantum dot/quantum well FETs and NVRAMs. Our simulations have shown 4-states/2-bit output-input transfer characteristics in SWS-CMOS inverters and NAND gates using two Si/SiGe quantum well channels.

Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.

This paper presents multi-state quantum dot channel (QDC) FETs incorporating cladded quantum dots forming a novel superlattice (QDSL) as the transport channel. Harnessing QDSL mini-energy band transitions as well as the encoding of spatial location of carriers in the upper or lower quantum dot channels is utilized to obtain 8- and 16-logic states. Potentially, 32-logic states can be achieved by additionally incorporating QDSL between tunnel oxide and gate. This maybe an interim alternative to sub-milliKelvin Si/SiGe qubits.

This paper presents a novel D-latch circuit using multi-state quantum dot channel (QDC) spatial wavefunction-switched (SWS) field-effect transistors (FET). The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in each channel. Spatial location is used to encode multiple logic states along with the carrier transport in mini-energy bands formed in GeO_x-Ge/ SiO_x-Si quantum dot superlattice (QDSL), and to obtain 8-states operation. The design is based on the 8-state inverter using QDC SWS-FETs in CMOS-X configuration. This could be a new paradigm for designing flip-flops and registering more complex sequential circuits. The proposed design leads to reduced propagation delay and a smaller Si footprint.

This paper presents multistate spatial wavefunction switched (SWS)-quantum dot channel (QDC) field-effect transistor (FET) static random access memory (SRAM)-based Compute-in-Memory (CIM) cell. The SWS-QDC FETs have two or more vertically stacked coupled quantum dot channels, and the spatial location of carriers within these channels is governed by the applied gate voltage. The location of the carriers can be utilized to encode multiple logic levels within a single device. The utilization of SWS-QDC FETs in CIM cell increases the data storage and energy-efficient computation in the memory. CIM reduces the data access time and improves performance for energy-efficient artificial intelligence (AI) edge devices.

Static random-access memory (SRAM) is an essential component in the architecture of modern microprocessors and VLSI circuits. The problems of high power consumption, large area, circuit complexity, and data stability against noise are among the most important indicators of performance and obstacles to the current use of SRAM. Ternary, quaternary, and higher-order logic (MLV) systems have shown the potential in overcoming these limitations in increasing the information density compared to the traditional binary system. The quantum dot channel field-effect transistor (QDC-FET) and quantum well Spatial Wavefunction Switched field-effect transistor (SWS-FET) are a new alternative with multiple operating states, low power consumption, and smaller footprints. This work presents a new four-state SRAM design that uses SWS-FET and compares it with Voltage-Mode CMOS Quaternary logic design. In addition, this work studies the noise margin in the memory circuit of the quadrilateral logic system and its effect on data stability. Furthermore, this study shows the reliability of quaternary SRAM design by evaluating the impact of errors.

Compared to multi-valued logic (MVL) with conventional 2-state FETs with a single threshold, MVL computing architectures, based on 4-state SWS (Spatial wavefunction switched) and QDG (quantum dot gate)-FETs having multiple thresholds, results in reduced device count, higher clock (CLK) speed, and lower power consumption. We have experimentally shown multi-state characteristics in SWS-FETs as well as QDG-FETs. This paper presents a novel QDG-SWS-FET that: (1) functions as a multi-bit FET for efficient low-power logic, (2) can be configured as a quantum dot (QD) nonvolatile random access memory (NVRAM), and (3) is suitable for in-memory MVL computing architecture that are compatible with sub-7nm technology nodes. A QDG-SWS-FET with the addition of a control gate dielectric layer functions as a NVRAM cell. Furthermore, it is shown that one single SWS-QD-NVRAM cell gives the functionality of a 1-bit NAND. We have developed circuit/device models and performed quantum simulations for novel multi-layer quantum dot/quantum well FETs and NVRAMs. Our simulations have shown 4-states/2-bit output-input transfer characteristics in SWS-CMOS inverters and NAND gates using two Si/SiGe quantum well channels.

Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.

This paper presents multi-state quantum dot channel (QDC) FETs incorporating cladded quantum dots forming a novel superlattice (QDSL) as the transport channel. Harnessing QDSL mini-energy band transitions as well as the encoding of spatial location of carriers in the upper or lower quantum dot channels is utilized to obtain 8- and 16-logic states. Potentially, 32-logic states can be achieved by additionally incorporating QDSL between tunnel oxide and gate. This maybe an interim alternative to sub-milliKelvin Si/SiGe qubits.

This paper presents a novel D-latch circuit using multi-state quantum dot channel (QDC) spatial wavefunction-switched (SWS) field-effect transistors (FET). The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in each channel. Spatial location is used to encode multiple logic states along with the carrier transport in mini-energy bands formed in GeO_x-Ge/SiO_x-Si quantum dot superlattice (QDSL), and to obtain 8-states operation. The design is based on the 8-state inverter using QDC SWS-FETs in CMOS-X configuration. This could be a new paradigm for designing flip-flops and registering more complex sequential circuits. The proposed design leads to reduced propagation delay and a smaller Si footprint.

This paper presents multistate spatial wavefunction switched (SWS)-quantum dot channel (QDC) field-effect transistor (FET) static random access memory (SRAM)-based Compute-in-Memory (CIM) cell. The SWS-QDC FETs have two or more vertically stacked coupled quantum dot channels, and the spatial location of carriers within these channels is governed by the applied gate voltage. The location of the carriers can be utilized to encode multiple logic levels within a single device. The utilization of SWS-QDC FETs in CIM cell increases the data storage and energy-efficient computation in the memory. CIM reduces the data access time and improves performance for energy-efficient artificial intelligence (AI) edge devices.

Static random-access memory (SRAM) is an essential component in the architecture of modern microprocessors and VLSI circuits. The problems of high power consumption, large area, circuit complexity, and data stability against noise are among the most important indicators of performance and obstacles to the current use of SRAM. Ternary, quaternary, and higher-order logic (MLV) systems have shown the potential in overcoming these limitations in increasing the information density compared to the traditional binary system. The quantum dot channel field-effect transistor (QDC-FET) and quantum well Spatial Wavefunction Switched field-effect transistor (SWS-FET) are a new alternative with multiple operating states, low power consumption, and smaller footprints. This work presents a new four-state SRAM design that uses SWS-FET and compares it with Voltage-Mode CMOS Quaternary logic design. In addition, this work studies the noise margin in the memory circuit of the quadrilateral logic system and its effect on data stability. Furthermore, this study shows the reliability of quaternary SRAM design by evaluating the impact of errors.