International Journal of High Speed Electronics and Systems

Plasmonic nanostructures with electrical connections have potential applications as new electro-optic devices due to their strong light–matter interactions. Plasmonic dimers with nanogaps between adjacent nanostructures are especially good at enhancing local electromagnetic (EM) fields at resonance for improved performance. In this study, we use optical extinction measurements and high-resolution electron microscopy imaging to investigate the thermal stability of electrically interconnected plasmonic dimers and their optical and morphological properties. Experimental measurements and finite difference time domain (FDTD) simulations are combined to characterize temperature effects on the plasmonic properties of large arrays of Au nanostructures on glass substrates. Experiments show continuous blue shifts of extinction peaks for heating up to 210°C. Microscopy measurements reveal these peak shifts are due to morphological changes that shrink nanorods and increase nanogap distances. Simulations of the nanostructures before and after heating find good agreement with experiments. Results show that plasmonic properties are maintained after thermal processing, but peak shifts need to be considered for device design.

Volatile organic compounds (VOCs) are ubiquitous in the surroundings, originating from both industrial and natural sources. VOCs directly impact the quality of both indoor and outdoor air and play a significant role in processes such as fruit ripening and the body’s metabolism. VOC monitoring has seen significant growth recently, with an emphasis on developing low-cost, portable sensors capable of both vapor discrimination and concentration measurements. VOC sensing remains challenging, mainly because these compounds are nonreactive, appear in low concentrations and share similar chemical structures that results in poor sensor selectivity. Therefore, individual gas sensors struggle to selectively detect target VOCs in the presence of interferences. Electronic noses overcome these limitations by employing machine learning for pattern recognition from arrays of gas sensors. Here, an electronic nose fabricated with four types of functionalized gold nanoparticles demonstrates rapid detection and quantification of eight types of VOCs at four concentration levels. A robust two-step machine learning pipeline is implemented for classification followed by regression analysis for concentration prediction. Random Forest and support vector machine classifiers show excellent results of 100% accuracy for VOC discrimination, independent of measured concentration levels. Each Random Forest regression analysis exhibits high R² and low RMSE with an average of 0.999 and 0.002, respectively. These results demonstrate the ability of gold nanoparticle gas sensor arrays for rapid detection and quantification.

This paper presents technology computer-aided design (TCAD) modeling of an enhancement-mode aluminum gallium nitride (AlGaN)/gallium nitride (GaN) high electron mobility transistor (HEMT) with extensive π-gate optimization for high-power and radio frequency (RF) applications. Effects of the gate voltages on threshold (V_th), transconductance (g_m), breakdown voltage (V_BR), cutoff frequency (f_T), maximum frequency of oscillation (f_max) and minimum noise figure (NF_min) are systematically investigated with different gate structures (π–Shaped p-GaN MISHEMT, π–Shaped p-GaN HEMT, π–Gate HEMT). A comparative study demonstrates that π–Gate with additional p-GaN and insulating layer makes the device effectively operate in the enhancement mode having a threshold voltage (V_th) = 1.72 V with a breakdown voltage (V_BR) = 341 V, exhibiting better gate control with maximum transconductance (g_m,max) of 0.321 S/mm. In addition, the proposed device architecture with an optimized gate structure maintains a balance between a positive device threshold and a high breakdown voltage and achieves a better noise immunity with the minimum noise figure of 0.64 dB while operating at 10 GHz with a cutoff frequency (f_T) of 33.4 GHz, and a maximum stable operating frequency (f_max) of 82.3 GHz. Moreover, the device achieved an outstanding V_th, g_m,max, V_BR, f_T, f_max and NF_min making it suitable for high-power, high-speed electronics, and low-noise amplifiers.

In this paper, we propose a scheme for high-speed all-optical Pseudo-Random Binary Sequence (PRBS) generator and use it for generating keystream for encryption. This PRBS generator design is based on Linear Feedback Shift Registers (LFSR) and optical XOR and AND gates. The optical logical gates are based on quantum dot-semiconductor optical amplifier Mach-Zehnder interferometer (QD-SOA-MZI). With two photon absorption (TPA) in quantum dot-semiconductor optical amplifier (QD-SOA), this kind of optical logic gates performs well when processing data in an ultra-fast timescale and therefore able to function as high speed PRBS generator. Result shows that it’s possible for this scheme to realize all-optical encryption and decryption at high process rate up to 320 Gb/s. We simulated different ways of generating keystream with schemes such as cascaded generator, parallel generator and alternating step generator. These generators use more than one LFSR. Result shows that the schemes we use can function as stable and complex keystream generators.

The fourth fundamental circuit element, the memristor, has become a promising candidate to substantially improve the energy and area efficiencies of circuits as traditional complementary metal-oxide-semiconductor (CMOS) technology is approaching its physical limit. However, a mathematical representation of the experimentally obtained current-voltage characteristic of the memristor is necessary to develop and test memristor-based circuitry in electrical design simulators. Here we have developed a behavioral model for the I-V trace of a Pt/TiO₂/Pt memristor that can relate the fitting equations with the physical processes associated with the device in response to applied electrical excitation. Multiple conduction mechanisms are involved in memristor that depend upon its latest state. Therefore, the I-V has distinct segments that altogether form a hysteresis loop pinched at the center. In accordance with the predominant conduction mechanisms at each segment, our model defines the form of the equations. The behavioral model can adequately represent the experimental I-V retrieved from existing work.

This paper presents a novel D-latch circuit using multi-state quantum dot channel (QDC) spatial wavefunction-switched (SWS) field-effect transistors (FET). The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in each channel. Spatial location is used to encode multiple logic states along with the carrier transport in mini-energy bands formed in GeO_x-Ge/ SiO_x-Si quantum dot superlattice (QDSL), and to obtain 8-states operation. The design is based on the 8-state inverter using QDC SWS-FETs in CMOS-X configuration. This could be a new paradigm for designing flip-flops and registering more complex sequential circuits. The proposed design leads to reduced propagation delay and a smaller Si footprint.

Optical pulses at high repetition rates are generated using rational harmonic mode locking and saturable absorber made of graphene nanoparticles in a fiber laser. The pulse generation from the fiber laser is modeled by solving the Generalized Nonlinear Schrodinger Equation. The computation involved varying the various saturable absorption parameters, such as linear and nonlinear absorption coefficients. Experimentally stable pulse trains at 20 GHz and 50 GHz are generated with a pulse width of ∼ 2.7 ps. This result agrees with the simulation.

A novel gain and index tailored (GIT) external cavity laser (ECL) is presented. The single frequency laser demonstrates high power operation in excess of 250 mW and shot noise limited relative intensity noise (RIN) at 100 mW. This laser source is an ideal source for intensity-modulated direct detection (IMDD) photonic links. Link budget analysis is completed based on measured RIN and optical power. The analysis demonstrates that there are significant radio frequency performance advantages to operating at higher optical power while maintaining low RIN.

This paper presents multistate spatial wavefunction switched (SWS)-quantum dot channel (QDC) field-effect transistor (FET) static random access memory (SRAM)-based Compute-in-Memory (CIM) cell. The SWS-QDC FETs have two or more vertically stacked coupled quantum dot channels, and the spatial location of carriers within these channels is governed by the applied gate voltage. The location of the carriers can be utilized to encode multiple logic levels within a single device. The utilization of SWS-QDC FETs in CIM cell increases the data storage and energy-efficient computation in the memory. CIM reduces the data access time and improves performance for energy-efficient artificial intelligence (AI) edge devices.

This paper presents preliminary results of a high speed 1550 nm indium gallium arsenide (InGaAs)-based mesa-type modified uni-traveling carrier photodiode (M-UTC-PD) structure. Conventional UTC-PD refers to P-I-N type photodiodes which selectively use electrons as active carriers. Photons absorbed in the relatively thin P-type absorber create minority carriers which are field accelerated toward a depleted collector thereby establishing high velocity ballistic transport, making these structures applicable for high speed applications. The M-UTC-PD structure presented uses spatially tailored P-type absorber regions to limit minority carrier generation both in the lateral and axial dimensions. Utilizing an otherwise conventional UTC-PD epitaxial structure where the top P-type layers are undoped, the spatially tailored P-type regions are defined by closed ampoule Zinc diffusion techniques. The M-UTC-PD structure presented utilizes a series of nested p-doped rings within a mesa structure to limit dark current and reduce overall capacitance to improve high speed operation. Two photodiode structures will be investigated for this research project, a conventional UTC-PD structure and a modified structure, utilizing similar device designs, epitaxial designs and fabrication processes. The conventional structure will be utilized for fabrication process development, verification of epi quality and development of rapid prototyping approach toward chip-based testing and subsequent high speed RF testing procedures. Conventional UTC-PD device results will be used as a comparison to quantify the performance of the M-UTC-PD structure utilizing Zn-doped defined p-type absorber regions. Results are given for chip tests of UTC-PD chips verifying epitaxial quality and fabrication process, subsequent testing of packaged devices and RF analysis remains. Process development of the Zn-doped devices is underway, once completed, these devices will be compared to the base design to quantify performance enhancement associated with the modified design.

Reservoir Computing (RC) is a type of machine learning inspired by neural processes, which excels at handling complex and time-dependent data while maintaining low training costs. RC systems generate diverse reservoir states by extracting features from raw input and projecting them into a high-dimensional space. One key advantage of RC networks is that only the readout layer needs training, reducing overall training expenses. Memristors have gained popularity due to their similarities to biological synapses and compatibility with hardware implementation using various devices and systems. Chaotic events, which are highly sensitive to initial conditions, undergo drastic changes with minor adjustments. Cascade chaotic maps, in particular, possess greater chaotic properties, making them difficult to predict with memoryless devices. This study aims to predict 1D and 2D cascade chaotic time series using a memristor-based hierarchical RC system.

As the crisis of confidence and trust in overseas foundries arises, the industry and academic community are paying increasing attention to Printed Circuit Board (PCB) security. PCB, the backbone of any electronic system hardware, always draws attackers’ attention as it carries system and design information. Numerous ways of PCB tampering (e.g., adding/replacing a component, eavesdropping on a trace and bypassing a connection) can lead to more severe problems, such as Intellectual Property (IP) violation, password leaking, the Internet of Things (IoT) attacks or even more. This paper proposes a technique of active self-defense PCB modules with zero performance overhead. Those protection modules will only be activated when the boards are exposed to the attacks. A set of PCBs with proposed protection modules is fabricated and tested to prove the effectiveness and efficiency of the techniques.

The rapid development and deployment of 5G/mm-Wave technologies for communication, sensing and energy harvesting applications have been on the rise. Consequently, the need for low-cost, scalable, agile and compact RF modules has become more prominent than ever. This paper presents a review of recent efforts in utilizing additive manufacturing techniques such as inkjet printing to sustainably accelerate the massive deployment of 5G/mm-Wave. First, a novel flexible and massively scalable multiple-input, multiple-output (MIMO) tile-based phased array enabled by additively manufactured microstrip-to-microstrip transitions is presented. Next, a novel Rotman-Based harmonic mmID tag for Ultra-Long-Range localization is presented. Finally, low-power, low-cost mm-Wave backscattering modules for localization and orientation sensing are demonstrated.

This paper presents fabrication of multi-state inverters incorporating SiO_x-cladded Si quantum dot in the channel and gate region of driver, load, and access transistors. Experimental characteristics are presented exhibiting 3-state behavior in Quantum-dot Channel (QDC)-Quantum-dot Gate (QDG) FETs having Si quantum dots. It is shown that QDC-QDG-FETs-based enhancement mode inverter configurations are the building blocks of a multi-bit static random access memory (SRAM). QDC-QDG-FETs exhibiting four states can also be used to implement compact 4-state logic and nonvolatile memories or random access nonvolatile memories.

This paper presents multi-state QDC-QDG FET structures that has the potential to introduce additional states (8 or 16) by utilizing additional mini-energy sub-bands. Mini-energy bands are formed in Si quantum dot channel (QDC) comprising two silicon oxide cladded Si quantum dots (QDs). Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of two Si QD layers in the gate region. With the addition of a control gate oxide layer, we transform the QDC-QDG-FET into a quantum dot (QD) nonvolatile random access memory (NVRAM). Quantum simulations are presented.

Microplastics are commonly recognized as environmental and biotic contaminants. The prevalent presence of microplastics in aquatic settings raises concerns about plastic pollution. Therefore, it is critical to develop methods that can eliminate these microplastics with low cost and high effectiveness. This review concisely provides an overview of various methods and technologies for removing microplastics from wastewater and marine environments. Dynamic membranes and membrane bioreactors are effective in removing microplastics from wastewater. Chemical methods such as coagulation and sedimentation, electrocoagulation, and sol-gel reactions can also be used for microplastic removal. Biological methods such as the use of microorganisms and fungi are also effective for microplastic degradation. Advanced filtration technologies like a combination of membrane bioreactor and activated sludge method show high microplastic removal efficiency.

This paper investigates the non-Fourier transient heat transfer in an SOI FinFET transistor. The calibrated drift-diffusion (D-D) model in conjunction with the ballistic diffusive (BDE) model is used as an electrothermal model to predict phonon and electron transports in the quasi-ballistic regime. The finite element method has been employed to generate the numerical results. The proposed mathematical formulation was found to capture the transfer characteristics and the temporal temperature as given by TCAD simulation and experimental data. On the other hand, we have demonstrated that after 100 ns, the 14 nm Bulk FinFET supports better temperature distribution than the 14 nm SOI FinFET.

We report experimental demonstration of Material Implication (IMP) logic using ZnO nanowire-based memristors. The logic is demonstrated with a high-to-low resistance ratio of only five. This imposes much less stringent requirements on memristor performance that can enable IMP logic operation with lower bit error rates. Process independence on memristor and memristor-based IMP logic performance is demonstrated, and a more practical implementation of logic is made by relaxing the restriction imposed on the ranges of the values of on and off state resistances. IMP logic is validated up to a clock frequency of 100 KHz.

A novel magnetostrictive thin film fiber sensor is presented which can be utilized in an interferometric architecture. The magnetostrictive fiber sensor utilizes novel fiber and thin film technology to achieve high sensitivity in the sub-nanotesla regime. The base sensor architecture utilizes optical fiber wound in a novel low stress flat coil resembling a record, coated with a thin magnetostrictive film. Two prototype variants were fabricated, incorporating FeCo sputtered films of different thicknesses on 4 μm polyimide jacket single mode fiber. The sensors were incorporated into a fiber optic interferometric measurement apparatus to characterize time-varying magnetic field sensitivity. Device results are presented which demonstrate sensitivity is a function of film thickness. The experimental data exhibited a two-order magnitude sensitivity improvement as the thin film thickness was doubled. Sensitivity projections are made based on film thickness.

This paper presents a study on the propagation delay and power dissipation of a 2-bit static random-access memory (SRAM) with two cross-coupled multi-state spatial wave function switching (SWS) CMOS inverters. The proposed SRAM design utilizes the advantages of the CMOS-SWS inverter, such as its small area, low power consumption, and high speed. The 2-bit SRAM circuit simulations were carried out in Cadence to analyze the power dissipation and propagation delay. An Analog Behavioral Model (ABM) and the Berkeley Short-channel IGFET Model (BSIM4.6) in 0.18-μm technology were combined to create this model. The analysis of the propagation delay shows that the multi-state CMOS-SWS SRAM significantly reduces the delay compared to other multi-state 6T SRAM memories. Additionally, the analysis of the power dissipation shows that the multi-state SWS-SRAM is comparable to conventional SRAMs. These results demonstrate the potential of multi-state SWS-SRAM for improving the performance of memory circuits and provide valuable insights for future design optimization.

A 30-GHz pulse-train is generated using the rational harmonic mode-locking technique, experimentally, using a Mach–Zehnder Lithium Niobate modulator. The width of the pulses is then reduced from 5.8-ps to 1.9-ps by incorporating nonlinear polarization rotation. This phenomenon arises due to the very high nonlinear behavior of the photonic crystal fiber (PCF) added to the ring laser cavity. Numerically solving the Generalized Nonlinear Schrödinger Equation provided insights into the pulse evolution behavior. The relative polarization angle and length of the PCF were varied to study their effects on the pulse-width.

A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.

This paper presents experimental I-V characteristics of a QDC-QDG FET that exhibited 5-states and has the potential to introduce additional states (e.g. 8) by utilizing Ge QDSL mini-energy sub-bands. Mini-energy bands are formed in an asymmetric Si quantum dot channel (QDC) comprising of two silicon oxide cladded Si quantum dots (QDs), where the upper layer has a smaller core diameter and thicker upper oxide cladding serving as tunnel oxide. Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of Si QD layers in the gate region. This paper also proposes Gate all around (GAA) FETs, when integrated with nonvolatile random access memories (NVRAMs) that have the potential for wafer scale integration, similar to vertical NANDs. Novel Si and Ge Quantum-dot-based device configurations discussed in this paper open the pathway forward to implement hardware platform for emerging applications using low power consumption and smaller footprint.