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An Integrated Circuit for Radio Astronomy Correlators Supporting Large Arrays of Antennas

Larry R. D’Addario

Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA 91109, USA

E-mail Address: ldaddario@jpl.nasa.gov

Corressponding author.

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and

Douglas Wang

Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA 91109, USA

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https://doi.org/10.1142/S2251171716500021Cited by:9 (Source: Crossref)

Abstract

Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. While the cost of most components of the telescope is proportional to the number of antennas N, the cost and power consumption of cross-correlation are proportional to $N^{2}$ and dominate at sufficiently large N. Here, we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In a large system, each IC performs correlations for all pairs of antennas but for a portion of the telescope’s bandwidth (the so-called “FX” structure). In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals (N=32 antennas with two opposite-polarization signals per antenna). When N is larger, the input data are buffered in an on-chip memory and the CMACs are reused as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the ICs size and power consumption. It is intended for fabrication in a 32nm silicon-on-insulator process, where it will require less than 12mm² of silicon area and achieve an energy efficiency of 1.76–3.3pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to $N = 4096$ . The system-level energy efficiency, including board-level I/O, power supplies, and controls, is expected to be 5–7pJ per CMAC operation. Existing correlators for the JVLA ( $N = 32$ ) and ALMA ( $N = 64$ ) telescopes achieve about 5000pJ and 1000pJ, respectively using application-specific ICs (ASICs) in older technologies. To our knowledge, the largest-N existing correlator is LEDA at $N = 256$ ; it uses GPUs built in 28nm technology and achieves about 1000pJ. Correlators being designed for the SKA telescopes ( $N = 128$ and $N = 512$ ) using FPGAs in 16nm technology are predicted to achieve about 100pJ.

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