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Because of chip fabrication outsourcing, piracy, reverse engineering, and counterfeiting are major concerns for the semiconductor industry as well as the government. To prevent these issues, Physical Unclonable Functions (PUFs) based methods have been proposed has a way to authenticate chips. PUFs extract randomness from the manufacturing variations of a device that is probabilistic in nature. PUFs are generally easy to implement, but, because of its random behavior, its response is hard to predict and model. Many existing PUF techniques such as arbiter and ring oscillator can be hard to implement inside a chip because of their large area overhead. Hence, we have proposed a novel low pass filter PUF design in this work based on the internal resistor and capacitor variations within an IC. We have simulated the setup in Cadence Virtuoso for a 45 nm technology node. The resultant output voltage of our proposed PUF will be different at the same cut-off frequency because of the manufacturing variations. Finally, the output of the low pass filter PUF is connected with an inverter to make the signal digital and after that, a digital counter is connected with the inverter to measure the pulse width that can be used for generating a unique PUF output.

An automated circuit analysis tool called SPICESoft, the main objective of which is to help designers in sensitivity computation and circuit analysis is presented. Three main features of SPICESoft are described, namely Sensitivity Analysis, Circuit Performance Analysis, and Inverse Circuit Performance Analysis. A new methodology called Binary Differential Expansion used for data interpolation is also described in this paper. The relationship between device and process parameters is covered. The simulation results obtained using the proposed automated tool are compared with those of conventional computation.

Yield maximization is an important aspect in the design of integrated circuits. A prerequisite for its automation is a reliable and fast worst performance analysis which results in corners that can be used in the process of circuit optimization. We formulate the constrained optimization problem for finding the worst performance of an integrated circuit and develop a direct search method for solving it. The algorithm uses radial steps and rotations for enforcing the inequality constraint. We demonstrate the performance of the proposed algorithm on real world design examples of integrated circuits. The results indicate that the algorithm solves the worst performance problem in an efficient manner. The proposed algorithm was also successfully used in the process of yield maximization, resulting in a 99.65% yield.

This paper discusses a hybrid Digital-Analog Converter (DAC) architecture which is a combination of a binary-weighted resistor approach for eight bits in the least-significant-bit and thermometer coded approach for four bits in the most-significant-bit. The proposed design combines advantages of the binary-weighted resistor approach and thermometer coded approach. The final design is composed of two 12-bit DACs to achieve a pseudo differential output signal. The converter was designed with a Silterra 0.18 μm 1.8 V/3.3 V CMOS process technology. The post-layout simulation results show that this design achieves 12-bit resolution with INL and DNL of 0.375 LSB and 0.25 LSB, respectively. The power consumption is 6.291 mW when the designed DAC is biased with supply voltage equal to 3 V. The performance is accomplished with a design area of 230 μm × 255 μm.

A new unity gain buffer architecture is presented for on-chip CMOS mixed signal applications. The proposed two-stage common source active load (CSAL) buffer with source feedback offers improved performance compared to previously published source follower and source-coupled differential-pair-based unity gain buffers. A 90-nm CMOS design ($V_{\mathrm{\text{dd}}}$ equals 1.2V) of the buffer has the following performance parameters. With $C_{\mathrm{\text{in}}}$/$C_L$ of 10 fF/250 fF, $f{}_{-3\mathrm{\text{dB}}}$ is 4.4GHz, low frequency gain is 0.16dB, maximum input range within 2% gain variation is 260mV, total harmonic distortion (THD) is $-$63.3dB, offset error (input offset minus output offset) is 26mV, and 1.06mW power consumption. The active load, low gain amplifiers eliminate stability issues and any need for compensation capacitors. The architecture facilitates a relatively large input/output voltage swing while keeping transistors operating in the saturation region, making it suitable for submicron technologies with low rail voltages.

Crosstalk effects in multilayer graphene nanoribbon (GNR) interconnects for the future nanoscale integrated circuits are investigated with the help of ABCD parameter matrix approach for intermediate- and global-level interconnects at 11nm and 8nm technology nodes. The worst-case crosstalk-induced delay and peak crosstalk noise voltages are derived for both neutral and doped zigzag GNR interconnects and compared to those of conventional copper interconnects. The worst-case crosstalk delays for perfectly specular, doped multilayer GNR interconnects are less than 4% of that of copper interconnects for 1mm long intermediate interconnects and less than 7% of that of copper interconnects for 5mm long global interconnects at 8nm node. As far as the worst-case peak crosstalk noise voltage is concerned, neutral GNR interconnects are slightly better performing than their doped counterparts. But from the perspective of overall noise contribution, doped GNR interconnects outperform neutral ones for all the cases. Finally, our analysis shows that from the signal integrity perspective, perfectly specular, doped multilayer zigzag GNR interconnects are a suitable alternative to copper interconnects for the future-generation integrated circuit technology.

The present methodology of clock distribution inside high-performance central processing unit chip offers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to $L$d$i$/d$t$. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current profile (current versus time), by controlling the current on all the complementary metal oxide semiconductor gates of the clock generation circuits. In our methodology, the time for the chip to reach the maximum saturation current is same when compared with the present linear current ramp methodology. We have also developed a new “optimizer program” to show the existence of a unique single current profile solution, which is different from the present methodology. The proposed method requires understanding of how the minimum value of the power supply voltage (supposed to be always 1V for the device) gets changed, when various gates in a clock tree are turned ON at different times ($T_n$, parameters of the problem) with different values of current ($I_n$, other parameters of the problem). Basically, an ensemble of “$n$” number of transistors will be turned ON at time $t=T_n$ while it will pump the total current $I=I_n$. This understanding generates the derivative function of the minimum noise point with respect to these said parameters, which in turn generates a new set of parameters to optimize the noise point. We have found that this optimizer program works and also converges for the generation of minimum power and ground noise, which is 40% lesser than the conventional approach.

The state-of-the-art development and subsequent miniaturization of technologies in e-systems such as computers and digital communication systems have led to densely and compactly placement of devices and interconnects in ICs. The incessant advancements of technologies have necessitated a rapid increase in operating frequencies. At nanometer dimensions and advanced technology nodes, the performance of the overall VLSI system is critically dominated by on-chip interconnects. Interconnects perpetuate several nonideal effects such as signal delay, power dissipation and cross-talk that limit the overall system performance. Owing to graving effect of interconnects on the performance parameters in ICs, research into interconnects has become meticulously very active in recent years, and concurrently much progress has been made. In this review paper, a literature review and contemporary advancements on conventional aluminum, copper and subsequent next generation graphene interconnects have been systematically presented.

Tunability of correlated color temperature (CCT) and dimmability are the two major sought after features of functional solid-state lighting. This paper presents a low-cost, efficient, single-inductor-dual-output buck driver that facilitates CCT-control and dimming of a light emitting diode (LED) module composed of cool-white and warm-white chips. The proposed driver is designed based on two familiar integrated circuits (ICs), namely LM2596 and NE556. LM2596 serves as the main switching regulator and amplitude modulation (AM) controller whereas NE556 serves as the constant-frequency, dual-output pulse-width-modulation (PWM) controller. The exponential model of LED is exploited for improved estimation of the design parameters of the LED module and the driver circuit. The developed driver prototype is tested for its electrical, photometric, and colorimetric performances. The driver offers a full-load efficiency of about 90% for a 12-W test LED module. Under different operating modes, the LED system can produce warm, cool, or neutral white light and at the same time, the produced illuminance can be varied over a wide range. Moreover, the light flicker is imperceptible since the PWM frequency is set according to IEEE-1789 guideline.

First-order allpass filters are analog filters with a unit magnitude response, but they change the phase shift between input and output signals at various frequencies. This paper presents the transadmittance-mode first-order allpass filters based on the modified current-controlled current differencing transconductance amplifier (M-CCCDTA). The proposed filters utilize a single M-CCCDTA and a grounded capacitor with no external resistors, making them well suited for implementation in an integrated circuit. The gain and phase response of the proposed filters can be adjusted electronically and separately. Also, the high output impedance of the proposed filters at both the input voltage node and the output current node makes cascading easy without the need for buffer devices. A quadrature sinusoidal oscillator based on the proposed first-order allpass filter has been designed as an example of an application. The PSpice simulation and actual experiments are utilized to validate the functionality of the proposed filters. The simulation and experimental results are consistent with the idea of anticipation.

This paper presents a novel footless single clock-phase three-stage comparator with internally generated regenerative voltage signals for low kickback noise and high speed. The preamplifier and clocked latch topology of dynamic comparators are considered in this brief. The proposed design has been compared by analyzing and optimizing three state-of-the-art comparator designs: Modified StrongARM, Miyahara’s and Three-Stage. These designs are simulated using the 40nm CMOS technology process. The area of the proposed comparator is 28.025$\mu$m². When simulated in the SPICE-based simulator HSPICE, under typical performance conditions of 0.9V supply voltage, 25^∘C, 1 GHz operational frequency, typical process corner (tt), and 1mV differential voltage, the proposed comparator produces the best post-layout results, with a minimum delay of 59.9ps from meta-stability analysis, energy per comparison of 0.175pJ/comparison and a kickback noise of 44.55 $\mu$A. The proposed design also shows a significant improvement in the measured performance parameters over the other state-of-the-art dynamic comparators that have been discussed in this brief. The obtained results show that the proposed comparator is appropriate for 12-bit Successive Approximation Resister Analog-to-Digital Converters (SAR-ADCs) in IoT applications.

In order to solve the problem that the test time is long and the test efficiency is affected in the process of IC test. With the increase in the complexity of integrated circuits, it is difficult now to diagnose the faults. To overcome this situation, there is a need to upgrade the test strategies. Based on the fault probability model, the order of test types and test vector is being adjusted. To improve the test efficiency, the high-quality test types and test vectors are loaded first, and the fault circuits are hit earlier. A hierarchical dynamic method for IC test flow is proposed. The Bayesian probability model was established by counting the failure rates of each test type and each test vector in the sample integrated circuit, and the loading sequence of each test vector was adjusted according to the probability of hitting the fault point. As the test progresses, the test data are collected constantly, the test failure rates of test type and test vector are dynamically updated, and the loading sequence of test type and test vector is adjusted synchronously. It is proved that the final circuit test time is reduced to 32.172s by the dynamic adjustment method, and the test time is reduced by 53.9%. The use of dynamically adjusted test process can find the fault circuit earlier, significantly reduce the test time of the fault circuit, and improve the test efficiency.

Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. While the cost of most components of the telescope is proportional to the number of antennas N, the cost and power consumption of cross-correlation are proportional to $N^2$ and dominate at sufficiently large N. Here, we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In a large system, each IC performs correlations for all pairs of antennas but for a portion of the telescope’s bandwidth (the so-called “FX” structure). In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals (N=32 antennas with two opposite-polarization signals per antenna). When N is larger, the input data are buffered in an on-chip memory and the CMACs are reused as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the ICs size and power consumption. It is intended for fabrication in a 32nm silicon-on-insulator process, where it will require less than 12mm² of silicon area and achieve an energy efficiency of 1.76–3.3pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to $N=4096$. The system-level energy efficiency, including board-level I/O, power supplies, and controls, is expected to be 5–7pJ per CMAC operation. Existing correlators for the JVLA ($N=32$) and ALMA ($N=64$) telescopes achieve about 5000pJ and 1000pJ, respectively using application-specific ICs (ASICs) in older technologies. To our knowledge, the largest-N existing correlator is LEDA at $N=256$; it uses GPUs built in 28nm technology and achieves about 1000pJ. Correlators being designed for the SKA telescopes ($N=128$ and $N=512$) using FPGAs in 16nm technology are predicted to achieve about 100pJ.

Because of chip fabrication outsourcing, piracy, reverse engineering, and counterfeiting are major concerns for the semiconductor industry as well as the government. To prevent these issues, Physical Unclonable Functions (PUFs) based methods have been proposed has a way to authenticate chips. PUFs extract randomness from the manufacturing variations of a device that is probabilistic in nature. PUFs are generally easy to implement, but, because of its random behavior, its response is hard to predict and model. Many existing PUF techniques such as arbiter and ring oscillator can be hard to implement inside a chip because of their large area overhead. Hence, we have proposed a novel low pass filter PUF design in this work based on the internal resistor and capacitor variations within an IC. We have simulated the setup in Cadence Virtuoso for a 45 nm technology node. The resultant output voltage of our proposed PUF will be different at the same cut-off frequency because of the manufacturing variations. Finally, the output of the low pass filter PUF is connected with an inverter to make the signal digital and after that, a digital counter is connected with the inverter to measure the pulse width that can be used for generating a unique PUF output.