Special Issue on Advances in Oscillator Analysis and Design; Guest Editors: A. S. Elwakil (Univ. of Sharjah, Emirates), T. Ueta (Tokushima Univ., Japan) and K. N. Salama (King Abdullah Univ. of Science and Technology, Saudi Arabia)No Access

A LOW-VOLTAGE SCALABLE (1.8 V–0.75 V) CMOS FOLDED-CASCODE LC QUADRATURE VCO FOR RF RECEIVERS

S. M. REZAUL HASAN

S. M. REZAUL HASAN

Center for Research in Analog and VLSI microsystem dEsign (CRAVE), School of Engineering and Advanced Technology (SEAT), Massey University, Albany, Auckland, Auckland 0632, New Zealand

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https://doi.org/10.1142/S0218126610006475Cited by:3 (Source: Crossref)

Abstract

This paper presents a scalable low voltage CMOS folded-cascode quadrature voltage controlled oscillator (QVCO) design for radio-frequency (RF) applications using the TSMC 0.18 μm 6M1P CMOS process technology. The simulated startup behavior of this proposed QVCO topology indicates that, the QVCO is free from bi-modal oscillation (frequency ambiguity). The QVCO provided extended voltage swing with the supply voltage scalable in the range of 1.8 V to 0.75 V. The QVCO operates in the frequency range of 4 GHz to 3 GHz (corresponding to supply voltage scaling in the range of 1.8 V to 0.75 V) with around 11.7% tuning range and low quadrature error. The QVCO had a power consumption under 10 mW within the specified supply voltage scaling range. Phase noise simulations using the Monte Carlo analysis provide an approximate phase noise estimate of ≈ -150 dBc/Hz at an offset of 600 KHz from the center frequency (@3.7 GHz) for operation using the 1.8 V supply voltage, using moderate inductor-Q values. Monte Carlo simulations were also carried out to determine the effects of the process, voltage and temperature variations.

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