Narrow Results

Noise widely exists in the nervous system, and plays an extremely important role in the information processing of the nervous system, which can enhance or weaken the ability of the nervous system to process information. Nerve cells exist in complex and changeable electromagnetic fields, and their potential changes are significantly regulated by electromagnetic induction. In response to this, first, a memristor is used to simulate the electromagnetic field environment where the nervous system is located, when using different weak periodic signals as the input of the neuron system, the rich stochastic resonance behavior of the FitzHugh–Nagumo neuron system is analyzed under the drive of phase noise. Second, taking the amplitude, period and intensity of phase noise as the main change parameters, and the changes of the parameters of the memristor and the period of the external signal as auxiliary conditions, the stochastic resonance dynamics analysis is carried out from three perspectives: the amplitude and period of phase noise, the amplitude and intensity of phase noise and the intensity and period of phase noise.

Entanglement purification is a vital protocol to produce a high-quality entangled state from an ensemble of identical states. Based on the particular scheme of entanglement purification [Phys. Rev. A87, 052316 (2013)], the effect of phase fluctuation is investigated. The convergence pattern of the initial states can be divided into two kinds of regions, corresponding to the purified outcomes being a maximally entangled state (MES) or a separable state. And there is the fractal-like structure near the boundary between these two regions. It is found that the phase noise plays a positive role in generating an MES for an initial states near some fractal boundary, which can only become the separable one if the noise is absent. It is also found that the minimal iteration steps to achieve the maximally entangled state with the phase noise can be decreased, which can save the resource in the protocol.

Phase noise-induced single coherence resonance (CR) has been reported in previous studies. It is reported here that double CRs can be induced in the FitzHugh–Nagumo (FHN) model by phase noise when the oscillation period of phase noise is much larger than the firing period of the FHN model. By analyzing peaks in the power spectrums for the fast voltage variable and the coefficient variations (CVs) of interspike interval (ISI) series, we find that double CRs corresponding to the frequency of phase noise and the firing frequency of the FHN model respectively appear at small and large noise intensities. This implies that there are double chances for the FHN model to take advantage of the benefits of phase noise. Possible causes of the single CR are also discussed.

Coherent population trapping (CPT) cesium frequency standard plays a significant role in precision guidance of missile and global positioning system (GPS). Low noise 4.596 GHz voltage controlled oscillator (VCO) is an indispensable part of microwave signal source in cesium frequency standard. Low-phase noise is also the most important and difficult performance indicator of VCO. Starting from phase noise analysis method proposed by Leeson, the formulas about the relationship between phase noise of output signal of oscillator feedback model and phase fluctuation spectrum of amplifier, phase noise of oscillator are derived in this paper. Finally, the asymptote model of microwave oscillator is proposed based on the formula derivation. The experiment shows that when the reverse bias voltage of variode is 1.8 V, the designed oscillation frequency of VCO is 4.596 GHz, the power is −1 dBm and the DC power consumption is 19.6 mW. The tendency of phase noise simulation curve and actual test curve conform to asymptote model. The phase noise in 1 and 10 kHz is, respectively, −60.86 and −86.58 dBc/Hz. The significance of the paper lies in determining the main factors influencing oscillator phase noise and providing guiding direction for the design of low-phase noise VCO.

Nowadays, some countries have already invented chip-scale atomic clock (CSAC) based on coherent population trapping (CPT), and it has been applied in every areas. According to its working principle, the microwave signal source is one of the decisive factors affecting its stability. Usually the microwave signal source is a phase-locked loop circuit, it mainly includes a frequency synthesizer, a voltage controlled oscillator (VCO) and a loop filter. This paper aims to develop a microwave signal source for Cs CSAC. First, a VCO should be designed, in order to validate the characteristic of the designed VCO, the VCO needs to be tested at high and low temperatures, and the results show that it has good stability of high and low temperatures. Second, for the purpose of verifying that the design and production consistency of the VCO are in good condition, 1000 VCOs are test, respectively. The statistical distribution of the phase noise at 1 kHz offset would be painted a curve. Finally, the designed VCO (PN: 61.01dBc/Hz@1kHz) will be applied in phase-locked loop, the test results show that the phase noise is −83.57dBc/Hz@300Hz, it is much better than −43dBc/Hz@300Hz which is the spec of CSAC. If the microwave signal source would be used in CSAC, its stability would be greatly improved.

The influences of phase noise together with autapse on the resonance dynamics in a modified FitzHugh–Nagumo (FHN) neuron are investigated by numerical simulation, where the neuronal model is in the environment of electromagnetic induction. First, it is found that phase noise can induce double coherence resonances, which is further confirmed to be robust to the feedback gain of induction current. Surprisingly, by individually changing the period of phase noise and the feedback gain, a resonance-like behavior also appears. Subsequently, the significant phenomenon of autapse-induced multiple coherence resonances is discovered. Moreover, the phenomenon of multiple coherence resonances can emerge at a broad parameter range of autaptic strength and autaptic delay.

Through introducing the ingredients of electromagnetic induction and coupled time delay into the original Fitzhugh–Nagumo (FHN) neuronal network, the dynamics of stochastic resonance in a model of modified FHN neuronal network in the environment of phase noise is explored by numerical simulations in this study. On one hand, we demonstrate that the phenomenon of stochastic resonance can appear when the intensity of phase noise is appropriately adjusted, which is further verified to be robust to the edge-added probability of small-world network. Moreover, under the influence of electromagnetic induction, the phase noise-induced resonance response is suppressed, meanwhile, a large noise intensity is required to induce stochastic resonance as the feedback gain of induced current increases. On the other hand, when the coupled time delay is incorporated into this model, the results indicate that the properly tuned time delay can induce multiple stochastic resonances in this neuronal network. However, the phenomenon of multiple stochastic resonances is found to be restrained upon increasing feedback gain of induced current. Surprisingly, by changing the period of phase noise, multiple stochastic resonances can still emerge when the coupled time delay is appropriately tuned to be integer multiples of the period of phase noise.

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

This paper proposes a novel readout interface for a high-precision silicon MEMS vibratory gyroscope. The readout interface contains a closed-loop self-resonating driving circuit and a low-noise open-loop capacitance sensing circuit. In order to achieve an overall optimization in noise performance, the noise in driving loop of the interface is analyzed in detail. After the noise optimization, the driving frequency stability achieves 0.93 ppm, the front-end capacitance resolution achieves 0.002 aF/$\sqrt{\mathrm{\text{Hz}}}$. The total zero bias instability achieves 3.82${}^{\circ }$/h, and angle random walk (ARW) achieves 0.014${}^{\circ }$/s/$\sqrt{\mathrm{\text{Hz}}}$.

This paper presents the analysis and experimental evaluation of a modified dual-loop phase-locked loop synthesizer, using the phase noise transfer functions resulting from the linear model of the synthesizer. The different arrangement in the high-frequency loop, in contrast to previous reported series-connected dual-loop topologies, offers various advantages, such as improved phase noise, finer resolution, and lower spurious levels. Discrete elements are used to implement a prototype system for testing. This adds to the flexibility of the design and allows for experimental optimization of the loop trade-offs. The synthesizer generates signals in the 4850 MHz to 5050 MHz range with a 10 MHz resolution and can match the specifications for wireless LANs operating at 5 GHz. The design resulted in a prototype with very good characteristics suitable for future integration.

Modern wireless communication poses the requirements of fast settling time, small channel width, and low phase noise to frequency synthesizer. ΣΔ fractional-N frequency synthesizer is widely adopted due to its excellent characteristics in these aspects. This paper presents a number of system issues and design considerations/tradeoffs which are involved in the design of such a frequency synthesizer from the system point of view. These considerations include selection of loop parameters, choice of key building blocks, and critical system performance issues like spurious tones, quantization noise, in-band phase noise, out-of-band phase noise, and frequency accuracy/resolution. Finally, the future possibilities are briefly analyzed.

This paper presents a scalable low voltage CMOS folded-cascode quadrature voltage controlled oscillator (QVCO) design for radio-frequency (RF) applications using the TSMC 0.18 μm 6M1P CMOS process technology. The simulated startup behavior of this proposed QVCO topology indicates that, the QVCO is free from bi-modal oscillation (frequency ambiguity). The QVCO provided extended voltage swing with the supply voltage scalable in the range of 1.8 V to 0.75 V. The QVCO operates in the frequency range of 4 GHz to 3 GHz (corresponding to supply voltage scaling in the range of 1.8 V to 0.75 V) with around 11.7% tuning range and low quadrature error. The QVCO had a power consumption under 10 mW within the specified supply voltage scaling range. Phase noise simulations using the Monte Carlo analysis provide an approximate phase noise estimate of ≈ -150 dBc/Hz at an offset of 600 KHz from the center frequency (@3.7 GHz) for operation using the 1.8 V supply voltage, using moderate inductor-Q values. Monte Carlo simulations were also carried out to determine the effects of the process, voltage and temperature variations.

This paper describes the design and implementation of an RF CMOS quadrature LC voltage-controlled oscillator in a 0.35 μm technology. The proposed oscillator employs the switched tail transistor topology and differential switch capacitor tuning to achieve low phase noise operation. A modified series coupling mechanism is used for quadrature signal generation with wide output signal swing. The oscillator core circuit was designed to operate with a 2.5 V power supply voltage with a 4 mA total supply current. Measurement results showed that the prototype oscillator could achieve a nominal oscillation frequency of 2.2 GHz with -110 dBc/Hz phase noise at 1 MHz offset frequency.

This paper presents a novel low power consumption, low phase noise, and high tuning range CMOS cross-coupled voltage-controlled oscillator (VCO). Using common mode double-pseudo-resistance technique in the proposed circuit leads to low power dissipation without degrading the phase noise. Additionally, band-switching capacitor array is employed in order to increase the tuning range. The schematic circuit of the proposed VCO is simulated in 0.18 μm 1P6M CMOS process and simulation results show high efficiency of the proposed circuit. The overall tuning frequency range is from 1.7 GHz to 3.18 GHz (59%) with tuning voltage variation range from 0 V to 1.5 V. The proposed VCO circuit has phase noise of -102.6 and -124.3 dBc/Hz at 100 KHz and 1 MHz offset frequency from the carrier, respectively, while consumes 1.98 mW power at 1.5 V supply voltage.

This paper aims at presenting an equation describing a relation between power consumption and phase noise of the widely used CMOS cross-coupled LC differential oscillator. This equation is derived by using periodic time-varying method and it relates oscillator's key performance parameters, e.g., oscillation frequency and amplitude, sideband spectrum and bias current, and CMOS process parameters. The validity of the proposed equation was confirmed by the periodic noise simulation available in the Cadence's Virtuoso Spectre Circuit Simulator.

A new high figure-of-merit (FOM) and low-phase-noise 20.73-GHz voltage-controlled oscillator is designed for K-band applications in this paper. The capacitive feedback technique is used for the low-phase-noise VCO design. The VCO can be tuned from 20.817 GHz to 20.266 GHz. The measured phase noise is -115.57 dBc/Hz at 1 MHz offset from the carrier frequency. The corresponding FOM is calculated to be -190 dBc/Hz. The VCO is implemented with the TSMC 0.18 μm one-poly-six-metal 1.7 V mixed-signal/RF CMOS technology, and the chip size is 0.51 × 0.74 mm².

This paper represents a new enhanced Colpitts oscillator, which is designed based on g_m-boosting of a conventional Colpitts oscillator. The proposed topology increases the negative resistant and enhances the start-up difficulty of the conventional Colpitts oscillator. This enables the Colpitts oscillator to operate in low-power consumption. Moreover, the differential and balanced structure helps limit even-order harmonics and degrades the common mode noise effects in output. The proposed circuit is designed using 0.18 μm technology and is simulated under 1.8 V supply voltage in advanced design system (ADS). Simulations show the output phase noise of -140 dBc/Hz at 1 MHz offset frequency when the operating frequency is 1 GHz.

In 2003, a digitally controlled oscillator (DCO) for cellular mobile phones was first proposed and demonstrated, and after that DCOs are widely used along with the rapid development of wireless communications. DCOs based on LC structure gain an advantage over ring oscillators in phase noise and thereby become research hotspot during the last decade. This paper presents a review of inductance capacitance (LC)-DCOs classified by circuit topologies and performance. For each DCO structure, the principle exposition and performance analysis are given in detail. Moreover, a comparison among all kinds of DCOs mentioned in this paper is presented in tabular form. Finally, we discuss the obstacle to the development of DCOs and the possible tendency for future work in summary.

Comparative Phase Noise analyses of common-source cross-coupled pair, Colpitts, Hartley and Armstrong differential oscillator circuit topologies, designed in 28 nm bulk CMOS technology in a set of common conditions for operating frequencies in the range from 1 GHz to 100 GHz, are carried out in order to identify their relative performance. The impulse sensitivity function (ISF) is used to carry out qualitative and quantitative analyses of the noise contributions exhibited by each circuit component in each topology, allowing an understanding of their impact on phase noise. The comparative analyses show the existence of five distinct frequency regions in which the four topologies rank unevenly in terms of best phase noise performance. Moreover, the results obtained from the ISF show the impact of flicker noise contribution as the major effect leading to phase noise degradation in nanoscale CMOS LC oscillators.

This paper presents a digital embedded test instrument (ETI) for on-chip phase noise (PN) testing of analog/RF integrated circuits. The technique relies on 1–bit signal acquisition and dedicated processing to compute a digital signature related to the PN level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140nm technology occupies only 7,885$\mu$m², which represents an extremely small silicon area. Hardware measurements are performed on an FPGA prototype that validates the proposed instrument.