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Approximate computing (AC) in arithmetic logic has become a viable option in applications requiring error tolerance in energy-efficient architectures. AC relied on approximate arithmetic functions to reduce delay, area, and power consumption while sacrificing accuracy to reduce delay, power, and area. In this research, a novel two approximate recursive multipliers (RMul-1, RMul-2) and an approximate adder have been designed to reduce power consumption, area, and computational delay in error-tolerant systems. The recursive multipliers utilize a combination of NOR, AND, half adder, and full adder gates to achieve low power and area-efficient designs. Furthermore, to reduce time, the approximation adder uses an optimal combination of AND, OR, and MUX gates. Furthermore, the cadence RTL compiler synthesizes the proposed multiplier using 28nm technology, and it is compared to previous approximation multipliers. Image processing applications are simulated, and the performance of the proposed multipliers is verified using simulations using the Xilinx ISE 13.2 tool. The proposed RMul designs outperform current techniques by up to 30.3% in area, 20.2% in power, and 43.9% in delay, according to experimental results. In addition, the suggested multipliers outperform existing multipliers in terms of SSIM and PSNR.

This paper proposes six novel approximate 1-bit full adders (AFAs) for inexact computing. The six novel AFAs namely AFA1, AFA2, AFA3, AFA4, AFA5, and AFA6 are derived from state-of-the-art exact 1-bit full adder (EFA) architectures. The performance of these AFAs is compared with reported AFAs (RAAs) in terms of design metrics (DMs) and peak-signal-to-noise-ratio (PSNR). The DMs under consideration are power, delay, power-delay-product (PDP), energy-delay-product (EDP), and area. For a fair comparison, the EFAs and proposed AFAs along with RAAs are described in Verilog, simulated, and synthesized using Cadences’ RC tool, using generic 180 nm standard cell library. The unconstrained synthesis results show that: among all the proposed AFAs, the AFA1 and AFA2 are found to be energy-efficient adders with high PSNR. The AFA1 has a total $\mathrm{\text{power}}=1.722$$\mu$W, $\mathrm{\text{delay}}=213$ps, $\mathrm{\text{PDP}}=0.3668$fJ, $\mathrm{\text{EDP}}=78.1285\times 10^{-27}$Js, $\mathrm{\text{area}}=36.59$$\mu$m², and $\mathrm{\text{PSNR}}=26.4292$dB. And the AFA2 has the total $\mathrm{\text{power}}=1.924$$\mu$W, $\mathrm{\text{delay}}=215$ps, $\mathrm{\text{PDP}}=0.4136$fJ, $\mathrm{\text{EDP}}=88.924\times 10^{-27}$Js, $\mathrm{\text{area}}=33.264$$\mu$m², and $\mathrm{\text{PSNR}}=26.4292$dB.

Most image processing applications are naturally imprecise and can tolerate computational error up to a specific limit. In such applications, savings in power are achieved by pruning the data path units, such as an adder module. Truncation, however, may lead to errors in computing, and therefore, it is always a challenge between the amount of error that can be tolerated in an application and savings achieved in area, power and delay. This paper proposes a segmented approximate adder to reduce the computation complexity in error-resilient image processing applications. The sub-carry generator aids in achieving a faster design while carry speculation method employed improves the accuracy. Synthesis results indicate a reduced die-area up to 36.6%, improvement in delay up to 62.9%, and reduction in power consumption up to 34.1% compared to similar work published previously. Finally, the proposed adder is evaluated by using image smoothing and sharpening techniques. Simulations carried out on these applications prove that the proposed adder obtains better peak signal-to-noise ratio than those available in the literature.

In the modern Block-chain and Artificial Intelligence era, energy efficiency has become one of the most important design concerns. Approximate computing is a new and an evolving field promising to provide energy-accuracy trade-off. Several applications are tolerant to small degradation in results, and hence tasks like image and video processing are candidates to benefit from Approximate Computing. In this paper, we propose a new design approach for designing approximate adders and further optimize the accuracy and cost metrics. Our approach is based on minimizing the errors while cascading more than one 1-bit adder. We insert $|\mathrm{\text{error}}|=1$ on specific locations to achieve a reasonable circuit minimization and reduce the $\mathrm{\text{error}}\times {\mathrm{\text{count}}}_{\mathrm{\text{gate}}}$ cost. We compare our design with exact adder and relevant state-of-the-art approximate adders. Through analysis and simulations, we show that our approach provides higher accuracy and far better performance compared with other designs. The proposed double bit approximate adder provides more than 25% savings in gate count compared with the exact adder, has a mean absolute error of 0.25 which is lowest among all the reference approximate adders and reduces the power-delay product by more than 60% compared to the exact adder. When employed for image filtering, the proposed design provides a ${\mathrm{\text{PSNR}}}_{\mathrm{\text{avg}}}$ of 96%, a ${\mathrm{\text{SNR}}}_{\mathrm{\text{avg}}}$ of 95% and a ${\mathrm{\text{SSIM}}}_{\mathrm{\text{avg}}}$ of 91% relative to the actual results, while the second best approximate adder only achieves 64%, 54% and 71% of these image quality metrics, respectively.