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Architects and designers must consider issues of sustainability, building regulations, as well as a multitude of subjective questions such as style and taste. They are asked to create spaces not just in consideration of expected user needs, but in anticipation of them, whilst simultaneously defending and substantiating the value of their design decisions. By contrast, there is a growing body of research examining person-environment interactions and how experiences are immediately affected by designed properties of spaces. The research approach of Architectural Cognition in Practice seeks to develop a robust bridge to link learnings about user cognition from academic disciplines such as spatial cognition, neuroarchitecture and environmental psychology into real-world design processes. Toward this, we propose a framework addressing three distinct streams of issues: (1) Fundamental research to increase our understanding of person–environment interactions and their impact on cognition, decision-making and experience; (2) Reflective research considering how (and how well) designers currently conceptualize their end-users in the design process; and (3) Translational research to equip design teams with knowledge and tools to be able to apply learnings from architectural cognition into their practice. We briefly overview each pillar of research and provide examples from our own pool of research to demonstrate how our framework and methodologies aim to tackle this stated divide between knowledge and practice.

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials (Ge, diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

In this paper, we present a new architecture to build grids that can execute parallel programs based on legacy code. This architecture is layer based and software component performances are validated with benchmarks. To illustrate the construction of a grid using the proposed architecture, we develop a case study that consists of a grid oriented to efficient execution of Java bytecode for which we validate and integrate legacy code of parallel linear algebra.

Multi-label learning (MLL) problems abound in many areas, including text categorization, protein function classification, and semantic annotation of multimedia. Issues that severely limit the applicability of many current machine learning approaches to MLL are the large-scale problem, which have a strong impact on the computational complexity of learning. These problems are especially pronounced for approaches that transform MLL problems into a set of binary classification problems for which Support Vector Machines (SVMs) are used. On the other hand, the most efficient approaches to MLL, based on decision trees, have clearly lower predictive performance. We propose a hybrid decision tree architecture, where the leaves do not give multi-label predictions directly, but rather utilize local SVM-based classifiers giving multi-label predictions. A binary relevance architecture is employed in the leaves, where a binary SVM classifier is built for each of the labels relevant to that particular leaf. We use a broad range of multi-label datasets with a variety of evaluation measures to evaluate the proposed method against related and state-of-the-art methods, both in terms of predictive performance and time complexity. Our hybrid architecture on almost every large classification problem outperforms the competing approaches in terms of the predictive performance, while its computational efficiency is significantly improved as a result of the integrated decision tree.

Data fusion has been defined as a process dealing with the association, correlation, and combination of data and information from multiple sources to achieve refined position and identity estimates for entities, and complete and timely assessments of related situations and threats, and their significance. This process (sometimes labeled a “technology”) is pervasive, i.e. capable of broad, multi-domain application. Indeed, data fusion has found extensive application in the commercial/industrial sector as well, in areas such as robotics and process control, and for numerous applications requiring intelligent, autonomous processes and capabilities. One of the purposes of this paper is to describe the evolving standard description of the data fusion process ascribed to by the U.S. Joint Directors of Laboratories (JDL) Data Fusion Subpanel (a Department of Defense organization), as well as components of the attendant lexicon and taxonomy.

While the specific definitions of a “situation assessment (SA)” and a “threat assessment (TA)” have proven to be problem-dependent for most defense applications, these notions generally encompass a large quantity of knowledge which reflect the (dynamic) constituency-dependency relationships among objects of various classes as well as events and activities of interest. Formulation of hypotheses about situations and threats is a process having the following properties:

• it employs many types of knowledge

• it must consider multiple, asynchronous activities

• multiple types of dynamic and static data must be processed

• numerous sub-networks of interest in the situation/threat picture (numerous constituency-dependency relationships) exist—this leads to feedforward/backward inferencing requirements

• information-processing strategies are required to produce estimates of aggregated force structures (given individual unit positions and identities), as well as aggregated behaviors (given individual events or activities)

• the situational or threat state is often ephemeral and thus temporal reasoning capabilities must be part of the process

The paper expands on the processes and techniques involved in SA and TA analysis, and describes, from various points of view, why the blackboard paradigm is properly applicable to problems of SA and TA analysis. This assessment includes various trade-off factors (features, benefits, and disadvantages or complexities) in applying blackboard concepts to data fusion related reasoning processes.

Specific research and development by the authors and synthesis of the results of a survey on data fusion applications (shown within) has led to the formulation of a recommended generic, ideal blackboard architecture for these defense problems described in the paper.

Reduction of power dissipation in digital circuits is a subject of research in industry and academia. A major component of power dissipation in modern microprocessors is due to their large interconnect networks which are responsible for the distribution of power and clocks as well as for the intra-chip communication. Communication is realized by data and address buses. In this paper we (i) discuss an analytical model for energy estimation in deep submicron buses, (ii) present statistical energy measures based on the analytical model, (iii) derive the energy limits of communication through buses, (iv) and introduce energy efficiency measures of communication.

This paper presents a novel application-specific field-programmable gate array (FPGA) architecture that satisfies efficient implementation of digit-serial DSP architectures on a digit wide basis. Digit-serial DSP designs have been an effective implementation method for FPGAs. To efficiently realize a digit-serial DSP design on FPGAs, one must create an FPGA architecture optimized for those types of systems. We examine the various circuits used in digit-serial DSP designs to extract their key features that should be reflected in the new FPGA architecture. We explain the design methodology, layout and implementation of the new digit-serial FPGA architecture. Digit-serial DSP designs using the digit-serial FPGA (DS-FPGA) are compared to those implemented on Xilinx FPGAs. We have estimated that the DS-FPGA are about 2.5~3 times more efficient in area and faster than the equivalent digit-serial DSP architectures implemented using Xilinx FPGAs.

This paper presents a modified implementation of QR decomposition for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) detection based on the Givens rotation method. The QR decomposition hardware is constructed using the coordinate rotation digital computer (CORDIC) algorithm operating with fewer gate counts and lower power consumption than do triangular systolic array (TSA) structures. Accurate signal transmission is essential to wireless communication systems. Thus, a more effective data detection algorithm and precise channel estimation method play vital roles in MIMO systems. Implementing data detection with QR decomposition helps reduce the complexity of MIMO-OFDM detection. Implementation results reveal that the proposed recursive QR decomposition (RQRD) architecture has lower clock latency than do TSA structures, and has a smaller hardware area than do Gram–Schmidt structures.

The Time-Multiplexed FPGA (TMFPGA) architecture can improve dramatically logic utilization by time-sharing logic but it needs a large amount of registers among sub-circuits for partitioning the given sequential circuits. In this paper, we propose an improved TMFPGA architecture to simplify the precedence constraints so that the number of the registers among sub-circuits can be reduced for sequential circuits partitioning. To demonstrate the practicability of the architecture, we also present a greedy algorithm to minimize the maximum number of the registers. Experimental results demonstrate the effectives of the algorithm.

Power gating (PG) is used to reduce leakage power by shutting down the power supply of the inactive block of the circuit. PG technique for finite state machine (FSM) is used to reduce not only leakage power but also the switching power of circuit. One FSM is partitioned into two sub-FSMs and encoded for minimizing total power for the power-gated design of the circuit. Depending on the state of the machine, at a time one sub-FSM is power gated by shutting off the power supply. There is a complete eradication of power in power-gated sub-FSM, but another one is in an active mode that continues to dissipate power. There is a scope to reduce leakage in active sub-FSM if the clock period is larger than the critical path delay of the combinational part of this sub-FSM. In this condition, there is a certain portion of the clock period which is idle and in this period PG may be used. The objective of this paper is to reduce power by applying PG at circuit level to the active sub-FSM, whereas, inactive sub-FSM is still power gated. This paper presents a new technique, called WCPG_IN_PG, which reduces the power of active sub-FSM (within the clock period) and power-gated FSM. By varying the frequency, power results are reported for different input combinations.

In deep learning, convolutional neural networks (CNNs) are a class of artificial neural networks (ANNs), most commonly applied to analyze visual imagery. They are also known as Shift-Invariant or Space-Invariant Artificial Neural Networks (SIANNs), based on the shared-weight architecture of the convolution kernels or filters that slide along input features and provide translation-equivariant responses known as feature maps. Recently, various architectures for CNN based on FPGA platform have been proposed because it has the advantages of high performance and fast development cycle. However, some key issues including how to optimize the performance of CNN layers with different structures, high-performance heterogeneous accelerator design, and how to reduce the neural network framework integration overhead need to be improved. To overcome and improve these problems, we propose dynamic cycle pipeline tiling, data layout optimization, and a pipelined software and hardware (SW–HW)-integrated architecture with flexibility and integration. Some benchmarks have been tested and implemented on the FPGA board for the proposed architecture. The proposed dynamic tiling and data layout transformation improved by 2.3 times in the performance. Moreover, with two-level pipelining, we achieve up to five times speedup and the proposed system is 3.8 times more energy-efficient than the GPU.

Time and energy is expended in switching between power modes (e.g., active, hibernate, sleep, etc.). Powering off cache is one major reason for this. When there is a switch in the power-mode involving cache power-off, the system spends time and energy in filling the cache with new data (inherent cache misses). In our technique, before powering off the cache, we save its state in Embedded DRAM and bring it back when the previous power mode is restored. Our experiments have showed that in a majority of cases the cache contents are too valuable to be erased. By saving the contents we can reduce switching speed and energy. We present a heuristic to save the most relevant cache contents so that power and delay overheads are minimized. To measure the area overhead a synthesizable VHDL model was designed.

Software Product-Line Engineering (SPLE) is composed of two areas, namely domain engineering and application engineering. Domain engineering is associated with product-line architecture, which is a core asset of the product-line. One of the key issues of the software product-line, especially in domain engineering, is handling the variability among product families. That is, variation management for the software product-line architecture determines the success of software development. Therefore, this paper proposes processes and artifacts to build the software product-line architecture and to manage uniform variability over the life cycle of software product-lines. Furthermore, a case study, namely, the Electronic Medical Record (EMR) system, is presented.

The concept of software architecture has recently emerged as a new way to improve our ability to effectively construct large scale software systems. However, there is no formal architecture specification language available to model and analyze temporal properties of complex real-time systems. In this paper, an object-oriented logic-based architecture specification language for real-time systems is discussed. Representation of the temporal properties and timing constraints, and their integration with the language to model real-time concurrent systems is given. Architecture based specification languages enable the construction of large system architectures and provide a means of testing and validation. In general, checking the timing constraints of real-time systems is done by applying model checking to the constraint expressed as a formula in temporal logic. The complexity of such a formal method depends on the size of the representation of the system. It is possible that this size could increase exponentially when the system consists of several concurrently executing real-time processes. This means that the complexity of the algorithm will be exponential in the number of processes of the system and thus the size of the system becomes a limiting factor. Such a problem has been defined in the literature as "state explosion problem". We propose a method of incremental verification of architectural specifications for real-time systems. The method has a lower complexity in a sense that it does not work on the whole state space, but only on a subset of it that is relevant to the property to be verified.

Today's supply chains increasingly involve complex sets of processes, objectives and constraints, and therefore agent-based architectures for supply chain management (SCM) become much more difficult to implement and maintain. The paper presents a multi-agent architecture for specifying, analyzing and developing SCM systems, in which asynchronous teams (A-Team) of problem solving agents exchange results within populations that provide effective management of information flows in supply chains, and cooperate to produce sets of non-dominated solutions that show the tradeoffs between objectives. Our approach distinguishes itself by improving problem-solving efficiency based on a diverse set of algorithms without complicated synthesis efforts, removing the focus from agent communication and coordination details, and improving reusability, flexibility and extensibility by supporting object-oriented and component-based programming style. We examine the effectiveness of the architecture through a real-world case study and experimental results.

Many decision tree algorithms were proposed over the last few decades. A lack of publishing standards for decision tree algorithm software produced a large time gap between algorithm proposals and their wider application in practice. Non-existence of common repository for storing algorithms and their parts led to a need to re-implement these algorithms from a scratch when they had to be implemented on a different platform. This makes the comparison between algorithms and their partial improvements vague. In addition, combinations and interactions between different algorithm parts haven't been analyzed thoroughly. Reusable component design of decision tree algorithms has been recently suggested as a potential solution to these problems. In this paper we describe an architecture for component-based (white-box) decision tree algorithm design, and we present an open-source framework which enables design and fair testing of decision tree algorithms and their parts. This architecture and developed platform can provide the research community with a common codebase for storing, designing, and evaluating decision tree algorithms (traditional, multivariate and hybrid) and their partial improvements. It is intended for data mining practitioners, algorithm and software developers, and as well for students, as a technology enhanced learning tool.

The collagen architecture of osteophytes has been investigated by immunolocalization of types I, II, III and X collagens. Types I and III were observed in the superficial layers, type II in the superficial and middle layers and type X at the cartilage-bone junction. This pattern of distribution suggests a "maturation" pathway from precursor cells at the surface to cells transforming into bone at the base. The collagen fibers appear to be oriented horizontally in the superficial layers and vertically in the middle or intermediate layers, thus mimicking the architectural arrangement in normal articular cartilage.

This paper describes findings from a four-year research study which used a mixture of qualitative and quantitative research methods to identify factors that facilitate social learning and collaborative knowledge development. Social learning includes those factors which enable transmission of knowledge and practice and which foster generative learning. This paper's specific focus is on the facilitators of team building that support knowledge sharing and knowledge development.

This paper draws on work previously published on the difference between knowledge and information by the author (2014) as well as research into management and systems design, to propose a model for what a knowledge management system (KMS) might be comprised of. It proposes an architecture comprising specific elements that must be in place for a system to be considered a “KMS”. These elements are further broken down into a range of components within those elements that may exist to contribute to the functioning of a KMS.

Trustworthy and reliable applications built using intelligent software agents aim to provide improved performance using its characteristics. Agents introduced in various architectures represent its functionality as functional elements of the architecture and shows the interaction between other components present in the architecture. The Internet of things (IoT) reveals as a frequent technology that allows accessing the physical objects present in the world. IoT systems utilize wireless sensor network to transmit and receive data by establishing communication. Wireless Sensor Networks transmits digital signals to the cyber-world for analyzing and processing the information into useful data by either formulating or communicating with the intelligent and innovative system. While talking about IoT and WSN, agents introduced in such environments assist in making decisions quickly by perceiving the input from the environment. The number of agents needed for an application depends upon the complexity of the problem. Multi-Agent architectures discussed in the article describe their association, roles, functionality and interaction. This paper gives a detailed survey of various agent/multi-agent learning architectures introduced over IoT and WSN. Moreover, this survey with the performance and the SWOT analysis on the Agent-based learning architecture helps the reader and paves a way to pursue research on Agent-based architectural deployment over IoT and WSN paradigms.