Narrow Results

The gathering over meeting nodes problem requires the robots to gather at one of the pre-defined meeting nodes. This paper investigates the problem with respect to the objective function that minimizes the total number of moves made by all the robots. In other words, the sum of the distances traveled by all the robots is minimized while accomplishing the gathering task. The robots are deployed on the nodes of an anonymous two-dimensional infinite grid which has a subset of nodes marked as meeting nodes. The robots do not agree on a global coordinate system and operate under an asynchronous scheduler. A deterministic distributed algorithm has been proposed to solve the problem for all those solvable configurations, and the initial configurations for which the problem is unsolvable have been characterized. The proposed gathering algorithm is optimal with respect to the total number of moves performed by all the robots in order to finalize the gathering.

This paper proposes a universal constructor implemented on a self-timed cellular automaton, which is a particular type of asynchronous cellular automaton. Our construction utilizes the asynchronous nature of the underlying cellular automaton in a direct way, as a result of which it is simpler than the conventional construction based on the simulation of a synchronous cellular automaton by an asynchronous cellular automaton. Our model employs 39 rotation-invariant rules and the state of each cell is encoded by 8 bits.

A source sends a piece of data (message), relayed to a receiver by n processes, some of which can be faulty. We assume that the number of faulty processes is at most f and that faulty processes exhibit a Byzantine behavior. A deciding agent has to make a decision concerning the source message, on the basis of results obtained from the receiver. The environment is totally asynchronous. An Asynchronous Byzantine Voting Mechanism is a method that enables the deciding agent to always correctly determine the source message in this scenario.

We show that there exists a correct Asynchronous Byzantine Voting Mechanism if and only if f < n/3. If this condition is satisfied, we provide such a mechanism. This result should be contrasted with the feasibility of synchronous voting mechansisms, in which the receiver can wait until all fault-free processes convey their values: for this scenario a correct voting mechanism exists whenever f < n/2.

Learning a fast global model that describes the observed phenomenon well is a crucial goal in the inherently distributed Vehicular Networks. This global model is further used for decision-making, which is especially important for some safety-related applications (i.e., the altering of accident and warning of traffic jam). Most existing works have ignored the network overhead caused by synchronizing with neighbors, which inevitably delays the time for agents to stabilize. In this paper, we focus on developing an asynchronous distributed clustering algorithm to learn the global model, where cluster models, rather than raw data points, are shared and updated. Empirical experiments on a message delay simulator show the efficiency of our methods, with a reduced convergence time, declined network overhead and improved accuracy (relative to the standard solution). This algorithm is further improved by introducing a tolerant delay. Compared to the algorithm without delay, the performance is improved significantly in terms of convergence time (by as much as 47%) and network overhead (by around 53%) if the underlying network is geometric or regular.

The Circular Electron Positron Collider (CEPC) is proposed as a Higgs boson and/or Z boson factory for high-precision measurements on the Higgs boson. The precision of secondary vertex impact parameter plays an important role in such measurements which typically rely on flavor-tagging. Thus silicon CMOS Pixel Sensors (CPS) are the most promising technology candidate for a CEPC vertex detector, which can most likely feature a high position resolution, a low power consumption and a fast readout simultaneously. For the R&D of the CEPC vertex detector, we have developed a prototype MIC4 in the Towerjazz 180 nm CMOS Image Sensor (CIS) process. We have proposed and implemented a new architecture of asynchronous zero-suppression data-driven readout inside the matrix combined with a binary front-end inside the pixel. The matrix contains 128 rows and 64 columns with a small pixel pitch of 25 $\mu$m. The readout architecture has implemented the traditional OR-gate chain inside a super pixel combined with a priority arbiter tree between the super pixels, only reading out relevant pixels. The MIC4 architecture will be introduced in more detail in this paper. It will be taped out in May and will be characterized when the chip comes back.

This paper presents a low-power low-voltage chopper stabilized discrete-time second-order feed-forward ΣΔ modulator with an asynchronous 4-bit successive-approximation-register (SAR) quantizer. The feed-forward topology will reduce the internal signal swing, relaxing the linearity and slew rate requirements for an operational amplifier (op-amp). The analog weighted summation of feed-forward paths is merged with the sampling capacitor array of a SAR quantizer to minimize the distortion and associated hardware overhead. To achieve low power consumption, a partially switched op-amp bias in weak inversion is used for the first integrator. The energy efficiency is further improved by the asynchronous SAR 4-bit quantizer. Moreover, the asynchronous scheme will reduce loop delay caused by the summation block, the quantizer and the data weighted averaging (DWA) circuit, improving circuit stability and lowering power consumption. A 0.13-μm CMOS experimental prototype achieves 84 dB dynamic range, 84 dB peak SNR and 82 dB peak SNDR over an input signal bandwidth of 10-kHz. The total power consumption of the modulator is 48 μW from a 0.8 V supply at an 800-kHz sampling rate.

The significant process, voltage and temperature (PVT) variations seen with modern technologies make strictly synchronous design inefficient. Asynchronous design with its flexible timing is a promising alternative, but prototyping is difficult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in principle but cannot safely handle metastability issues that are inevitable even at some interfaces in asynchronous designs. In this paper, we propose reliable implementations of the fundamental function blocks required to safely convert potential intermediate voltage levels that result from metastability into late transitions that can be reliably handled in the asynchronous domain. These are high- and low-threshold buffers as well as a Schmitt-trigger. We give elaborate background analysis for the proposed circuits and also present the associated routing constraints to make the Schmitt-trigger circuit work properly in spite of the uncertain routing within FPGAs. Furthermore, we propose a procedure for an “in situ reliability assessment” of the specific Schmitt-trigger element under consideration, which also applies to metastability containment with high- or low-threshold buffers only. Our proof of concept is based on experimental results for both Xilinx and Altera FPGA platforms.

This paper proposes a high-voltage high-efficiency peak-current-mode asynchronous DC–DC step-down converter operating with dual operation modes. The asynchronous buck converter achieves higher efficiency in light load condition compared to synchronous buck converters. Furthermore, the proposed buck converter switches operation mode automatically from pulse-width modulation (PWM) mode to pulse-skipping mode (PSM). By reducing power MOS on-state resistance and optimizing rise/fall time of switches, the proposed buck converter also obtains high efficiency under heavy load condition. The maximum efficiency of the proposed buck converter is 92.9%, implemented with 0.35$\mu$m BCDMOS 2P3M process, and the total size is 1.1$\times$ 1.2mm². The input range and output range of the converter are 6–30 V, and ($V_{\mathrm{\text{input}}}$–3) V, respectively, with the maximum output current of 3 A. Moreover, its built-in current loop leads to good transient response characteristics. Therefore, it can be used widely in communication system and 12 V/24 V distributed power system.

The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of the external clock pulse. The outputs from the comparator are given to a XOR logic whose outputs serve as an internally generated clock (ready signal) to trigger the digital control block. Hence, an external clock is not required to initiate the digital control block making its operation asynchronous. By implementing this, the ADC can circumvent the usage of an oversampled clock and can operate on a single low-speed sample clock. This, in turn, saves power and it cuts down the required resilience in sampling rates. The proposed ADC has been designed and simulated using UMC-0.18$\mu$m CMOS technology which dissipates 32.18$\mu$W power when operated on a single 1V power supply and achieves complete 8-bit conversion in 1.09$\mu$s. The relative accuracy of capacitor ratio, aperture jitter and FOM are 0.39$\%$, 1.2ns and 125fJ/conversion-step, respectively.

In the present technology development billions of transistors are fabricated on a single chip, which improves the performance of circuits in terms of high data transmission speed and power consumption. This requirement of data transmission speed is achieved with the help of high-speed transceivers. In this paper, we present a high-speed asynchronous wave-pipelined serializer and deserializer (SerDes) transceiver implemented using current-mode logic (CML). This asynchronous transceiver circuit does not require a clock and therefore it saves large amount of power which is consumed in the phase locked loop (PLL) and frequency synthesizer circuits. Further, the proposed design is built using CML which saves more power. CML circuit operates at relatively higher speed as compared to CMOS circuits which helps the circuit to operate at higher data rate. Compared to conventional CML latch, a novel CML latch is proposed in our design to increase the speed. The circuit is implemented in standard CMOS 65-nm technology. The total power consumed by the serializer and deserializer is 9.32mW, which is very less as compared to published related works. The proposed asynchronous SerDes transceiver operates at 18.1-Gbps data transmission rate with low power dissipation.

Some patterns of synchrony/asynchrony in the dynamics of coupled cell systems can be predicted by symmetry. However, in the system without symmetry, the different patterns of periodic solutions may exist as well. We consider a general model including three cells with multiple time delays that connect in any possible manner. Our approach is based on the analytic construction by using a perturbation procedure together with the Fredholm alternative theory. Then we employ the Poincaré–Lindstedt series expansion to compute the Floquet exponents which determine the stability. Finally, we resort to numerical computation to get some insights about the leading term in the Floquet exponents, and the numerical simulations are given to confirm the theoretical results.

This paper presents results on the dynamics of asynchronous irregular cellular automata (as representations of natural information-processing systems). It is an approach to explaining global dynamics from local dynamics without the use of unrealistic intermediate structure (i.e., without synchronization or regular communication). The unrealistic intermediate structure is replaced by the the realistic assumption that local behavior is entropy reducing (an idea of E. Schrödinger).

It has been shown that, for systems composed of cells programmed as cyclic finite-state automata, the observed global oscillation can be explained in terms of the structure of attractors in the global state space. The degree of local connectivity (i.e., of communication between cells) is shown here to determine the size of global attractors, and in turn the sharpness of global behavior. However, the primary result here is the extension of these results to systems whose cells are programmed as arbitrary strongly connected automata. Finally, these phenomena are demonstrated by the simulations.

This paper reports a method that fuses multiple sensor measurements for location estimation of an underwater robot. Synchronous and asynchronous (AS) implementation of the method are also proposed. Extended Kalman filter (EKF) is used to fuse four types of measurements: linear velocity by Doppler velocity log (DVL), angular velocity by gyroscope, ranges to acoustic beacons, and depth. The EKF approach is implemented in three ways to deal with asynchrony in measurements in correction step. The three implementation methods are synchronous collective (SC), synchronous individual (SI), and AS application. These methods are verified and compared through simulation and test tank experiments. The test reveals that the application methods need to be selected depending on the measurement properties: dependency between the measurements and degree of asynchrony. The distinctive features proposed in this study are three application methods together with derivation of an EKF approach to sensor fusion for underwater navigation.