Narrow Results

A comprehensive SPICE model is developed for single photon avalanche diodes (SPADs). The model simulates both the static and dynamic behaviors of SPADs. Parameters of the model were extracted form experimental data obtained from SPADs designed and fabricated in a standard 0.5μm CMOS process. In this model, the resistive behavior of the device was modeled with an exponential function. Moreover, the device simulated response to incident optical power stimulation is modeled. Experimentally extracted parameters were incorporated into the model, and simulation results agreed with the experimental data.

This work presents a single chip integrated pulse generator-modulator to be utilized in a short range wireless radio sensors remote control applications. The circuit, which can generate single pulses, modulated in BPSK, OOK, PAM, and also PPM, has been developed in a standard CMOS technology (AMS 0.35 μm). Typical pulse duration is about 1 ns while pulse repetition frequency is until 200 MHz (5 ns "chip" time). The operating supply voltage is ± 2.5 V, while the whole power consumption is about 15 mW. Post-layout parametric and corner analyses have confirmed the theoretical expectations.

In this paper, a new mixed mode full-wave rectifier which consists of a current differencing transconductance amplifier (CDTA), resistor and two complementary MOS transistor is presented. The proposed circuit is called as mixed mode because it can be used as current-, voltage-, transimpedance- and transconductance-mode rectifier depending on how the resistor is connected to the input or output of the circuit. The presented circuit has an appropriate zero crossing performance, linearity, low component count, and can be adapted to modern IC technologies. It is also suitable for monolithic integrated implementation. LTSPICE simulations with 0.18 μm CMOS model obtained through TMSC are included to verify the workability of the proposed circuit. We also performed noise and Monte Carlo analyses. Various simulation results are presented to show the effectiveness of the proposed circuit.

This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18$\mu$m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8dB. The input and output reflection coefficients both are lower than $-10.0$dB over 2.5–11.5GHz. The input third-order intercept point (IIP3) is 5.6dBm at 8GHz and the noise figure (NF) is lower than 4.0dB. The LNA consumes 5.4mW power under a 1V supply voltage.

This paper presents results regarding the progress achieved in the design of a customized encrypted multiplexer cell. The focus of our interest is the no short-circuit dynamic differential logic method that demonstrates high immunity of a standard logic cell to the side channel attacks (SCAs). Three innovative solutions are examined and the best one is proposed for the encrypted multiplexer cell. Designed cells are realized to the layout masks level targeting the 350nm CMOS process. The post-layout simulations showed high resistivity to the SCA for all designed cells. The resistance to the SCA of the proposed design was statistically verified at the transistor level. The verification is performed using the Monte Carlo (MC) simulation in which widths and lengths of the transistor channel were varied according to the Gaussian distribution. The designed encrypted cell will be the part of a more complex crypto system for power consumption metering which should increase overall system’s data security.

Modern decananometer-sized MOS transistors tend to exhibit high rates of failure, underscoring the need for accurately estimating the unreliabilities of circuits built from such transistors. This paper presents a methodology for unreliability calculation that extends from individual transistors to complete logic circuits. As a logic cell’s or logic circuit’s unreliability is highly dependent on its transistors’ drain–source and gate–source voltages, SPICE simulations are used to determine the voltages for the individual transistors. The voltage measurements are then utilized by the mathematical equations to predict the unreliabilities with high accuracy. A scalable framework based on the proposed methodology has been successfully implemented. The framework has been validated using ISCAS85 benchmark circuits.

This paper presents a low-power, OOK-modulated, impulse-radio ultra-wideband (IR-UWB) transmitter. The pulse generation method is derived from a filtered combined edge technique, where narrow pulses are produced by a delay-and-logic gate and shaped with a filter to generate UWB pulses compliant with the FCC standard. The pulse-shaping filter and antenna driving circuit are co-designed and combined into one, that is, a pulse amplifying and shaping circuit that operates in the C-class state, resulting in extremely low complexity, low power, and small circuit area. The proposed IR-UWB transmitter was implemented and fabricated using a standard 0.18-$\mu$m complementary metal oxide semiconductor (CMOS) 1p6m process. The power supply voltage is 1.5V and the targeted maximal data rate is 250Mbps. The chip measurement results show that the output UWB signal covers 3.1–6.0GHz frequency band, the power spectrum density conforms to the FCC spectrum masks, and the peak-to-peak voltage of the output UWB pulses is 183mV. In addition, the core area of the chip is 0.098mm² and the transmitter power consumption is 2.48pJ per pulse.