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Multiplication plays an important role in digital signal processing. Reducing the power consumption in multipliers will bring significant power reduction to the overall digital system. (7,3) counters are one of the components that are used in parallel multipliers though it is not so popular as the (4:2) compressor. Several (7,3) counters have been reported but most of them are implemented in conventional CMOS style. In this paper, a low power (7,3) counter based on adiabatic switching principles is proposed. HSPICE simulations show that it achieves huge power savings than the static CMOS counterpart.

Power dissipation is one of the important issues in VLSI design. Reversible logic has zero power dissipation; therefore, nowadays, researchers attend to it in order to optimize the internal power consumption. On the other hand, fault tolerance is a solution for error detection in digital systems. In many systems, fault tolerance is achieved by parity checking. This article proposes a new parity-preserving reversible full adder circuit. For many years, researchers assumed that the quantum cost (QC) of the parity-preserving reversible full adder is 11. In this article we offered a new parity-preserving reversible full adder circuit with a QC of only 9. In addition, the proposed parity-preserving reversible full adder has optimum number of constant inputs and garbage outputs. A novel parity-preserving reversible 4:2 compressor circuit is also proposed using the proposed parity-preserving reversible full adder. This article would be a great initiation for building more complex parity-preserving reversible circuits. All the scales are in the nanometric area, and their fundamental parts are no bigger than a few nanometers.

As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25dB for image processing; similarly, with a decrease of 0.3dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.

Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.

In the era of low-power very large-scale integration design, approximate computing is a soaring design paradigm that assures energy-efficient circuit design at the cost of some accuracy. Multiplication is a very important operation of an arithmetic unit and compressor is the inherent part of the multiplier. In this paper, an energy-efficient design of a 4:2 approximate compressor is proposed. The inclusion of the extra leakage control transistors in the logic has led to leakage power reduction, which ultimately reduces the power dissipation in the circuits. The proposed 4:2 compressor is simulated at 10nm fin-field effect transistor (FinFET) technology. The proposed compressor has been verified for its functionality and robustness. The proposed design shows a power dissipation of 154.48nW and a delay of 9.16ps. In comparison to other 4:2 approximate compressors, the proposed compressor shows the least power dissipation, the lowest power delay product (PDP) and the highest robustness. The power dissipation of the proposed compressor is 92.84% less than that of the base compressor. The PDP of the designed compressor is 80.58% less than the minimum PDP among other compressors. The aging analysis for the negative bias temperature instability (NBTI) effect is also checked for the proposed compressor and compared with the existing designs.

Diverse applications in today’s digital era have a high demand for low-power, faster, and high-performance arithmetic circuits. In a multiplier, the power is the costliest part of carrying out partial products. A compressor type of adder is used for faster operation and has lesser power consumption. In this paper, a low-power, energy-efficient 4:2 compressor design has been presented. The proposed design is based on multi-threshold logic. A capacitive network has been used at the input side instead of resistors for better circuit operations. The CNFET-based network is used to design the same. Powers, delay, PDP, and EDP of the proposed design have been computed. It is observed that with 32nm CNFET technology it shows a maximum improvement in PDP and EDP of 69% and 70%, respectively. Moreover, extensive performance analyses against power supply, channel length, temperature, load, and operating frequency have been presented. Finally, the proposed compressor is applied to design Wallace’s multiplier which shows that it outperforms all other designs considered in this study. This indicates that the proposed compressor is quite useful for low-power VLSI circuits and systems applications.

This paper proposes two novel approaches: a signed–unsigned modified Booth decoder/encoder that is used for the production of partial products and a 5-2 compressor for the addition stage of partial products. The improvement of a circuit can be done at the transistor level and the gate level. To improve the circuits at the gate level for the modified Booth decoder/encoder, a new table was designed and also the 5-2 compressor was obtained by changing the truth table. Speed, power consumption and area were improved in the proposed structures. In this paper, at the transistor level, the gate diffusion input (GDI) technique was used to implement logical gates and the gate-level delay of the GDI structures was also calculated. The results indicated that the proposed 5-2 compressor had a delay of 119 ps with a power consumption of 65$\mu$W, which shows a 23.5% improvement in power delay product (PDP) compared to the best structure in the comparison table, whereas the proposed Booth decoder/encoder had a delay of 257 ps with a power consumption of 61.74$\mu$W and shows a 63.7% improvement in PDP compared to previous studies. By using the proposed structures in the multiplier, a 22% improvement in PDP was observed. To simulate the obtained structures, the TSMC 0.18 and 0.09$\mu$m technologies and the HSPICE software were used. Cadence software was used to implement the layouts of the proposed structures.