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Multiplication plays an important role in digital signal processing. Reducing the power consumption in multipliers will bring significant power reduction to the overall digital system. (7,3) counters are one of the components that are used in parallel multipliers though it is not so popular as the (4:2) compressor. Several (7,3) counters have been reported but most of them are implemented in conventional CMOS style. In this paper, a low power (7,3) counter based on adiabatic switching principles is proposed. HSPICE simulations show that it achieves huge power savings than the static CMOS counterpart.

Power dissipation is one of the important issues in VLSI design. Reversible logic has zero power dissipation; therefore, nowadays, researchers attend to it in order to optimize the internal power consumption. On the other hand, fault tolerance is a solution for error detection in digital systems. In many systems, fault tolerance is achieved by parity checking. This article proposes a new parity-preserving reversible full adder circuit. For many years, researchers assumed that the quantum cost (QC) of the parity-preserving reversible full adder is 11. In this article we offered a new parity-preserving reversible full adder circuit with a QC of only 9. In addition, the proposed parity-preserving reversible full adder has optimum number of constant inputs and garbage outputs. A novel parity-preserving reversible 4:2 compressor circuit is also proposed using the proposed parity-preserving reversible full adder. This article would be a great initiation for building more complex parity-preserving reversible circuits. All the scales are in the nanometric area, and their fundamental parts are no bigger than a few nanometers.

As many digital signal processing (DSP) applications such as digital filtering are inherently error-tolerant, approximate computing has attracted significant attention. A multiplier is the fundamental component for DSP applications and takes up the most part of the resource utilization, namely power and area. A multiplier consists of partial product arrays (PPAs) and compressors are often used to reduce partial products (PPs) to generate the final product. Approximate computing has been studied as an innovative paradigm for reducing resource utilization for the DSP systems. In this paper, a 4:2 approximate compressor-based multiplier is studied. Approximate 4:2 compressors are designed with a practical design criterion, and an approximate multiplier that uses both truncation and the proposed compressors for PP reduction is subsequently designed. Different levels of truncation and approximate compression combination are studied for accuracy and electrical performance. A practical selection algorithm is then leveraged to identify the optimal combinations for multiplier designs with better performance in terms of both accuracy and electrical performance measurements. Two real case studies are performed, i.e., image processing and a finite impulse response (FIR) filter. The design proposed in this paper has achieved up to 16.96% and 20.81% savings on power and area with an average signal-to-noise ratio (SNR) larger than 25dB for image processing; similarly, with a decrease of 0.3dB in the output SNR, 12.22% and 30.05% savings on power and area have been achieved for an FIR filter compared to conventional multiplier designs.

Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.

In the era of low-power very large-scale integration design, approximate computing is a soaring design paradigm that assures energy-efficient circuit design at the cost of some accuracy. Multiplication is a very important operation of an arithmetic unit and compressor is the inherent part of the multiplier. In this paper, an energy-efficient design of a 4:2 approximate compressor is proposed. The inclusion of the extra leakage control transistors in the logic has led to leakage power reduction, which ultimately reduces the power dissipation in the circuits. The proposed 4:2 compressor is simulated at 10nm fin-field effect transistor (FinFET) technology. The proposed compressor has been verified for its functionality and robustness. The proposed design shows a power dissipation of 154.48nW and a delay of 9.16ps. In comparison to other 4:2 approximate compressors, the proposed compressor shows the least power dissipation, the lowest power delay product (PDP) and the highest robustness. The power dissipation of the proposed compressor is 92.84% less than that of the base compressor. The PDP of the designed compressor is 80.58% less than the minimum PDP among other compressors. The aging analysis for the negative bias temperature instability (NBTI) effect is also checked for the proposed compressor and compared with the existing designs.

Diverse applications in today’s digital era have a high demand for low-power, faster, and high-performance arithmetic circuits. In a multiplier, the power is the costliest part of carrying out partial products. A compressor type of adder is used for faster operation and has lesser power consumption. In this paper, a low-power, energy-efficient 4:2 compressor design has been presented. The proposed design is based on multi-threshold logic. A capacitive network has been used at the input side instead of resistors for better circuit operations. The CNFET-based network is used to design the same. Powers, delay, PDP, and EDP of the proposed design have been computed. It is observed that with 32nm CNFET technology it shows a maximum improvement in PDP and EDP of 69% and 70%, respectively. Moreover, extensive performance analyses against power supply, channel length, temperature, load, and operating frequency have been presented. Finally, the proposed compressor is applied to design Wallace’s multiplier which shows that it outperforms all other designs considered in this study. This indicates that the proposed compressor is quite useful for low-power VLSI circuits and systems applications.

This paper proposes two novel approaches: a signed–unsigned modified Booth decoder/encoder that is used for the production of partial products and a 5-2 compressor for the addition stage of partial products. The improvement of a circuit can be done at the transistor level and the gate level. To improve the circuits at the gate level for the modified Booth decoder/encoder, a new table was designed and also the 5-2 compressor was obtained by changing the truth table. Speed, power consumption and area were improved in the proposed structures. In this paper, at the transistor level, the gate diffusion input (GDI) technique was used to implement logical gates and the gate-level delay of the GDI structures was also calculated. The results indicated that the proposed 5-2 compressor had a delay of 119 ps with a power consumption of 65$\mu$W, which shows a 23.5% improvement in power delay product (PDP) compared to the best structure in the comparison table, whereas the proposed Booth decoder/encoder had a delay of 257 ps with a power consumption of 61.74$\mu$W and shows a 63.7% improvement in PDP compared to previous studies. By using the proposed structures in the multiplier, a 22% improvement in PDP was observed. To simulate the obtained structures, the TSMC 0.18 and 0.09$\mu$m technologies and the HSPICE software were used. Cadence software was used to implement the layouts of the proposed structures.

Quantum and reversible logic circuits have found emerging attentions in nanotechnology, optical computing, quantum computing, and low power CMOS design. In this paper, we propose some new quantum and reversible compressors using our new genetic algorithm-based simulator, analyzer, and synthesizer software. The proposed quantum 4:2 and 6:2 compressor circuits are compared with the existing counterparts in terms of number of constant inputs, number of garbage outputs, delay and the quantum cost (QC). We have also designed quantum 7:2 compressor for the first time. The proposed quantum compressors are optimized in terms of QC and delay. The proposed designs can be used as a basic block in complex systems like multipliers, and can execute complicated operations better than the existing designs in literature.

In spite of the increase of the concern on electric vehicles (which is called green cars) and electrically driven automotive air conditioning system, the conventional automotive air conditioning system for internal combustion engines has been still investigated widely due to the realistic consideration. This paper is intended to include many automotive air conditioning system articles published in 1997 to 2013. This review, although extensive cannot include every paper; some selection is necessary. Reviewed papers herein are related to the research and development on effective design and performance improvement for the automotive air conditioning system and components, including theoretical, numerical, analytical and experimental works. Therefore, a number of published articles about the automotive air conditioning system, which contain the belt-driven compressors, heat exchangers and refrigerants, were considered. Many researches have focused on improving the efficiency of automotive air conditioning system to decrease the usage rate of the internal combustion engines.

An experimental investigation has been carried out to know about the performance improvement of a household refrigerator using phase change material (PCM). PCMs are used as latent heat thermal storage system to enhance the heat transfer of the evaporator. PCM is located behind the five sides of the evaporator cabinet in which the evaporator coil is immersed. Water (melting point 0°C) and Eutectic solutions (melting point −5°C) are used as PCMs for this experiment at different thermal loads. Depending on the types of PCM and thermal load, around 20–27% COP improvement of the refrigeration cycle has been observed with PCM with respect to without PCM. With the increase of the quantity of PCM (0.003 to 0.00425 m³) COP increases about 6%. Between two different PCMs the COP improvement for Eutectic solution is higher than Water. The experimental results with PCM confirm that, depending on the thermal load and the types of PCM average compressor running time per cycle is reduced significantly and it is found about 2–36% as compared to without PCM.

The application of biogas powered refrigeration system is being studied because of many folds increase in the cost of conventional fuels. This paper presents a numerical study of biogas operated ammonia–water hybrid vapor compression absorption refrigeration system for onsite dairy cooling applications. This system involves the compressor between the generator and condenser and use biogas (generated from the cattle dung) fired boiler to heat water which acts as an energy source for generator in the hybrid system. The variation of performance parameters such as heat load of different components, exergy loss, COP_cooling, COP_heating and exergy efficiency are studied with varying generator temperature. The results indicate that COP_cooling as well COP_heating values are in the range of 0.1125–0.2159 and 1.112–1.169, respectively, for the same variation in the generator temperature from 65°C to 130°C. The work done by the compressor is also calculated and found to be decreasing with an increase in the condenser, evaporator and generator temperature. The effect of the ambient temperature on the exergy loss in different components is also studied in the analysis and the results revealed that the maximum exergy loss is found in the generator and it is found to be the lowest in compressor.

This paper proposes a pseudo bond graph model of thermal transfers by natural convection inside a household refrigerator. It has two inputs: the ambient temperature and the temperature at the level of the evaporator wall. The latter assesses the functioning of the compressor cycles. A performance comparison, with the experimental data, was carried out in order to verify the model, in which, real measurements are used to modulate the evaporator temperature source. The simulation results show the effectiveness of the proposed approach.

The effects of oil wettability on the performance of a cyclone-type oil separator was studied through in situ experimentation and in a real refrigeration system. Based on previous research, the geometry of the oil separator in the present study was designed with an oil recovery device installed at its bottom to mount it on the actual refrigerator. The performance of the oil separator without surface treatment was predicted by applying design correlations proposed in the open literature, which were then compared with the experimental data. Through surface treatment, oleophilic or oleophobic properties were given to the inner wall and helix of the oil separator, and its performance was measured in a real refrigeration system. Oil wettability had a great effect on the performance of the oil separator, and in order to obtain high separation efficiency, oleophilic properties were found to be advantageous not only in the inner wall but also in the helix.

This paper presents the development of a numerical, iterative and nonisentropic model for the thermodynamic processes of a reciprocating compressor of a refrigeration system operating at steady state. The mathematical model was implemented using the scientific software Engineering Equation Solver (EES) and it is based on the application of the energy equations in four regions of the compressor: inlet duct and chambers of pre-compression, compression, and post-compression. The model was validated with experimental data collected from an open-drive reciprocating compressor, operating with the refrigerant R-134a at different suction and discharge pressures and with different compressor rotational speeds. Model validation was made comparing the values of the mass flow rate and the discharge temperature of the compressor generated by the model with their corresponding experimental values for 33 experimental tests, the mean relative difference was $-$0.2% for the discharge temperature and 2.9% for mass flow rate. In this validation, the output variables of the model were calculated considering the uncertainties from the input variables. The theoretical mean standard uncertainty is 2% for discharge temperature and 6% for mass flow rate. An analysis of the capacitive and thermal performance of the compressor was made using the model, which demonstrates a decrease in the capacitive and thermal efficiencies for increasing the pressure ratio or clearance volume.

With transistors reaching nanometer dimensions, dissipated energy has become of great importance in recent years. A practical approach to reducing energy consumption is to use logic-in-memory (LIM) structures based on magnetic tunnel junction (MTJ) devices combined with approximate computing. In this paper, we propose energy-efficient MTJ/FinFET-based approximate 5:2 compressors for error-resilient in-memory computing, providing an accuracy close to the exact design (1.54% error rate) while reducing the energy consumption by more than 50%. The innovative Boolean equations and the structure of the proposed approximate circuits based on spin-Hall effect assisted MTJs lead to a significantly more effective compromise between energy and accuracy than the previous exact and approximate counterparts. The simulation results provided using HSPICE with 7nm FinFETs and SHE-assisted MTJ models demonstrate the superior hardware parameters of the proposed designs. Furthermore, the MATLAB simulations show an average peak signal-to-noise ratio (PSNR) of more than 43 and an average structural similarity index metric (SSIM) of more than 0.99 across image multiplication, sharpening, and smoothing operations.

Shrinking the transistor dimensions in complementary metal-oxide-semiconductor (CMOS) technology has led to many huge problems, like high power density. Various methods at different design levels of abstraction, such as approximate computing and spintronic devices based on magnetic tunnel junction (MTJ), have been studied to solve these problems. In this paper, we propose a novel hybrid MTJ/FinFET-based approximate 5:2 compressor. The proposed design employs the spin-transfer torque (STT) method assisted by the spin-Hall effect (SHE) to store inputs in MTJs. Due to the SHE assistance, the energy efficiency of the MTJ switching is improved considerably over the conventional STT method. Our design significantly improves the energy consumption compared to the previous compressors, thanks to the decrease in MTJ and transistor counts. The proposed circuit and previous designs are simulated using HSPICE with 7-nm FinFET and SHE perpendicular-anisotropy MTJ model. From the simulation results, we can see that the proposed design improves power consumption, write energy, read energy, number of transistors and MTJ count on average by 49%, 50%, 63%, 20% and 50%, respectively, in comparison with the existing counterparts. Furthermore, the accuracy of the approximate designs is evaluated through comprehensive MATLAB simulations. The results indicate that the proposed circuit outperforms the best previous energy-efficient designs in terms of accuracy despite having better hardware characteristic parameters.

The following sections are included:

• Laser Fundamentals
• General Construction of a Laser
• Constructing Ultrafast Pulsed Laser
• Chirped Pulse Amplification (CPA)
• Amplifier
• Reference
• Further Reading

An aerodynamic optimization design study of a transonic compressor blade is carried out based on the three-dimensional parametric approach of local shape function. To avoid too many design variables and repeated mesh generation of optimized blade compare to the traditional approach in blade optimization. Mesh deformation technique of the reduced control points based on radial basis functions (RBF) is proposed, which combined with gradient based optimization algorithm, to solve the blade optimized problem. Analysis showed that: RBF mesh deformation technology could largely shorten the time of mesh generation without reducing the quality of meshes; the computational time was reduced greatly due to the gradient based optimization algorithm; the optimized blade increases the total pressure ratio by 0.86%, the adiabatic efficiency by 1.79% and the mass flow by 0.6% under the condition of consistent certain pressure outlet. The improvement of blade performance mainly is owing to the decrease of passage shock intensity.

In this paper, according to the application practice of scroll compressor for refrigeration and air-conditioning, various factors affecting the whole refrigeration effect of the compressor are studied, the influence of scroll wrap's different forms on compressor exhaust angle and the compression ratio is stated, and it establishes the working principle simulation of the compressor's main parts, and further corrects the form of vortex lines according to simulation results.