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Behavior models are proposed for HSPICE simulation of first-, second- and third-generation current conveyors. They can be used to speed up the exploration and verification of current conveyor-based circuit designs. To demonstrate the feasibility and workability of the proposed HSPICE simulation models, they are used as the current measuring devices for grounded and floating current sensing, and the simulation results are consistent with the theoretical expectation. The flexibility in the current sensing capability of the CCIII is also shown by a practical example using the behavior model. HSPICE simulation results are given.

Due to its programmable threshold-voltage characteristic, the floating-gate MOS transistor (FGT) plays an important role in the low-power applications. To tune the threshold voltages of FGTs accurately, a real-time system is presented to measure the threshold voltages. The system includes decoders, analog multiplexers, threshold-voltage measurement block, A/D converter and 32-bit advanced RISC machine (ARM). The feedback technique is applied so that the threshold voltages of FGTs can be measured with high accuracy. The measurement error lies in the range of ±0.3% with 16-bit A/D converter, and there has no constraint on the choice of capacitances between floating-gate and control-gate. The proposed measurement system does not require any matched component. The mathematical models of threshold-voltage measurement block are also presented. Thus, the accuracy of threshold-voltage measurements can be verified with these models.

In this paper, a floating inductance and frequency-dependent negative resistance (FDNR) depending on the passive element selection is presented. The proposed circuit employs only plus-type second-generation current conveyors (CCII+s) as active elements, together with two resistors and two capacitors for realizing floating inductance and FDNR. Both of the capacitors in the floating inductance realization are grounded. Also, electronically tunable floating FDNR is obtained with the proposed circuit. The nonideality effects of the current conveyors on the proposed circuit are given. The proposed circuit is used in a low-pass ladder filter, and simulated with SPICE to exhibit its performance.

A five-port general-purpose analog building block, termed as an Operational Floating Current Conveyor (OFCC), is described. The OFCC combines the features of current feedback operational amplifier, second-generation current conveyor and operational floating conveyor. An implementation scheme of the OFCC is described and its terminal operational characteristics are used to yield a working device. The OFCC is then used as a single block to realize the current conveyors (CCII+ and CCII-) as well as the four basic amplifiers (i.e., voltage, current, transconductance, and transresistance amplifiers). The applications of the OFCC are presented and discussed. In the field of the analog filter synthesis, we proposed a new active universal second order filter using OFCC. It has three inputs and one output employing two OFCC, two capacitors and three resistors and can realize lowpass, bandpass, highpass, notch, and all pass filters from the same configuration. The proposed universal filters offer the following advantageous features: using active elements for the same type (OFCC). No requirement for component matching or cancellation constraints, which makes the filter easier to design, orthogonal adjustment of ω₀ and Q and the circuits have low sensitivity. The simulation and experimental results are obtained and discussed.

In this paper, we introduce an implementation of a CCII-based grounded inductance operating in class AB. In order to get tunable characteristics of the design, a translinear CCII configuration is used as a basic block for its high level of controllability. A frequency characterization of the translinear CCII is done. In order to optimize its static and dynamic characteristics, an algorithmic driven methodology is developed ending to the optimal transistor geometries. The optimized CCII has a current bandwidth of 1.28 GHz and a voltage bandwidth of 5.48 GHz. It is applied in the simulated inductance design. We first consider the conventional topology of the grounded inductance based on the generalized impedance converter principle. Making use of the controllable series parasitic resistance at port X in translinear CCII, we design tunable characteristics of the inductance. The effect of current conveyor's nonidealities has been taken into account. A compensation strategy has been presented. It is based on the insertion of a high active CCII-based negative resistance and a very low passive resistance. The compensation strategy does not affect the inductance tuning process. Simulation results show that the proposed inductance can be tuned in the range [0.025 μH; 15.4 μH]. The simulated inductance has been applied in a fully integrated tunable high frequency band pass filter to illustrate the versatility of the circuit. The filter is electrically tunable by controlling the conveyor's bias current.

A simple 1.5 V rail-to-rail CMOS current conveyor is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and HSPICE is used to verify the circuit performance. The current conveyor exhibits low impedance at terminal X (7.2 Ω) and can drive ± 0.6 V to the 300 Ω with the total harmonic distortion of 0.55% at the operating frequency of 3 MHz. The voltage transfer error (between the Y and X terminals) and current transfer error (between the X and Y terminals) are small (-0.2 dB). The power dissipation and bandwidth are 532 μW and over 300 MHz, respectively.

The realization of the Tow–Thomas (TT) circuit using the Operational Transresistance Amplifier (OTRA) is reviewed. The circuit employs two OTRA, and all passive elements are floating as the original Tow–Thomas circuit. The Current Conveyor (CCII) TT circuits are reviewed next. The progress in the realization of the TT circuit using CCII is demonstrated clearly by summarizing eight different circuits. One of the circuits has the advantage of very high input impedance using all grounded resistors and capacitors. The Differential Voltage Current Conveyor (DVCC) as the active building block in realizing the TT circuit is also considered. Finally, current mode TT circuits using balanced output CCII are summarized. Top Spice (level 49), simulation results using technology SCN 05 feature size 0.5 μm from MOSIS vendor: AGILENT are included to demonstrate the magnitude and phase frequency response of the TT circuits. Additional simulation results for the total power dissipation, total harmonic distortion, intermodulation IM3, input and output referred noise spectral densities are also included for comparison purposes.

In this paper, a novel circuit for realizing voltage-mode first-order and second-order all-pass filter responses as well as second-order notch filter response depending on the passive component choice, is presented. This circuit has high input impedance; thus, it is easy to cascade the introduced filter with other voltage-mode topologies. Also, it uses a single Variable Gain Current Conveyer — VGCCII and only grounded capacitors. SPICE simulation results based on 0.35 μm TSMC CMOS technology parameters are given to confirm the theory.

A fully programmable second-order universal filter with independently controllable characteristics is presented in this paper. The proposed filter is based on a new ± 0.75 V second-generation current conveyor with digitally programmable current gain. The input stage of the current conveyor is realized using two complementary MOS differential pairs to ensure rail-to-rail operation. The output stage consists of a Class-AB CMOS push-pull network, which guarantees high current driving capability with a 47.2 μA standby current. The digital programmability of the current conveyor, based on transistor arrays and MOS switches, provides variable current gain using a digital code-word. Two approaches for implementing current conveyors with programmable current gain either greater or less than one are described. The fully programmable universal filter and the proposed digitally programmable current conveyor circuits are simulated using PSPICE with 0.25 μm CMOS technology from MOSIS.

Two new types of floating current conveyors are introduced. Each type has four ports: Y, X and two Z ports. The first type is the Floating Second Generation Current Conveyor (FCCII) and includes both CCII+ and CCII- as special cases. The second type is the Floating Inverting Second Generation Current Conveyor (FICCII) and includes both ICCII+ and ICCII- as special cases. The Nodal Admittance Matrix (NAM) stamp for the Nullator-Pathological Current Mirror is derived. Examples are given together with a CMOS circuit realizing both the FCCII and FICCII.

A new generation method of the Tow-Thomas (TT) circuit based on the nodal admittance matrix (NAM) expansion is given. The family of TT circuits defined includes four different types of generated circuits. All the advantages of the classical TT circuit namely, independent control on the frequency, selectivity factor Q and gain, besides having very low passive sensitivities are maintained. Besides, each of the family members of the generated circuits use grounded passive elements and has very high input impedance. It is found that there are eight circuits in each type implying a total of 32 TT circuits using current conveyors (CCII) and inverting current conveyors (ICCII). 24 circuits are new and four of them have a floating property.

The admittance matrix expansion method based on using nullors and pathological mirror elements is used to provide a systematic synthesis method of controlled sources. Four new realizations of the current controlled voltage source (CCVS) using a single grounded resistor are given. Three new nodal admittance matrix expansions (NAM) for the voltage controlled voltage source (VCVS) are introduced in this paper. The voltage mirror current mirror pair is used as intrinsic element in the NAM expansion. Eight new realizations for the noninverting VCVS using two grounded resistors are given. Eight realizations for the inverting VCVS using two grounded resistors are also given. Two new NAM expansions for the current controlled current source (CCCS) are introduced in this paper. The voltage mirror current mirror pair is used as an intrinsic element in the NAM expansion. Eight realizations for the CCCS using two grounded resistors are given. The generation of the controlled sources using a single building block is also discussed and the adjoint relations between VCVS and CCCS are summarized.

A new single input and five outputs high input impedance voltage-mode universal biquadratic filter using three DVCCs, five passive components is presented. The proposed circuit offers the following features: high input impedance, realization of all the standard filter functions, that is, high-pass, band-pass, low-pass, band reject and all-pass filters simultaneously, the use of grounded capacitor, orthogonal control of ω₀ and Q, no need to employ inverting type input signals, and no need to impose component choice except realizing the all-pass filter signal. A new quadrature oscillator circuit is also realized. PSPICE simulations using 0.35 μm TSMC CMOS parameters confirm the validity of the proposed circuit.

An integrated current mode high impedance input stage designed for Electrocardiography (ECG) systems (or low frequency general applications) is presented. This feature becomes necessary when a two-electrodes ECG apparatus is used (e.g., in fetal ECG or heart monitoring in extreme sports) and a good response of the system to common mode signals is required. The proposed input stage, based on a bootstrap topology that simultaneously increases the ECG electrodes input impedance (from 5 ÷ 50 kΩ to about 50 MΩ) and amplifies the applied signal, is implemented by using a configuration that employs only two second generation current conveyors for each electrode. Post-layout simulations have proved that the proposed system is quite not sensible to electrodes mismatch and battery discharge.

A new, self-biasing, differential pair-based and high performance CMOS CCII circuit is proposed which uses no additional biasing voltage or current sources other than the two supply rails. The proposed circuit has high voltage swings on ports X and Y, very low equivalent impedance on port X, high equivalent impedances on ports Y and Z and also wideband voltage and current transfer ratios. The noise analysis of the proposed CCII circuit is studied. Input referred noise voltage at high impedance port Y and input referred noise current at low impedance port X are obtained to form the noise model. Some filter circuits are selected from the literature and their noise comparisons are performed. It is shown that the noise values can differ greatly even though the filter circuits or the passive element values are identical.

This paper presents two new first-order voltage-mode (VM) cascadable all-pass (AP) sections, employing two differential voltage current conveyors (DVCCs) and three grounded passive components. Both circuits possess high input and low output impedance, which makes them easily cascadable. Non-ideality aspects and parasitic effects are also studied. As an application, a quadrature oscillator is designed using the proposed circuit. The proposed circuits are verified through PSPICE simulations using 0.5 μm CMOS parameters.

This paper presents a versatile universal current-mode and transresistance-mode biquadratic filter using only two multiple outputs second-generation current conveyors (MOCCIIs), two grounded capacitors, and three grounded resistors. The proposed configuration can realize all five standard filtering functions from one current-output terminal and one voltage-output terminal, and also provide all these filtering functions from different current-output and voltage-output terminals without changing the filter topology. Moreover, the proposed biquad filter still achieves many advantages like the employment of all grounded passive components, and the minimum number of active component counts, in addition to having no need of inverting-type input signals or double-type input signals for the use of special input signals, high output impedance and low sensitivity performance. H-Spice simulation results confirm the theory.

A current-mode universal biquadratic filter with three input terminals and one output terminal is presented. The architecture uses two current conveyors (CCs), two grounded capacitors and two grounded resistors; and can realize all standard second-order filter functions — highpass, bandpass, lowpass, notch and allpass. Moreover, the circuit still offers the following advantage features: very low active and passive sensitivities, using of grounded capacitors and resistors which is ideal for integrated circuit implementation, without requirements for critical component matching conditions and very high output impedance. The workability of the proposed circuit has been verified via HSPICE simulations using TSMC 0.18 μm, level 49 MOSFET technology.

In this paper, a digitally programmable OTA-based multi-standard receiver baseband chain is presented. The multi-standard receiver baseband chain consists of two programmable gain amplifiers (PGA1 and PGA2) and a fourth-order LPF. The receiver is suitable for Bluetooth/UMTS/DVB-H/WLAN standards. Three different programmable OTA architectures based on second generation current conveyors (CCIIs) and Current Division Networks (CDNs) are discussed. The programmable OTA with the lowest power consumption, moderate area and good linearity — better than -50 dB HD3 — is selected to realize the multi-standard baseband receiver chain. The power consumption of the receiver chain is 6 mW. The DC gain varies over a 68 dB range with 1 MHz to 13.6 MHz programmable bandwidth. The receiver baseband chain is realized using 90 nm CMOS technology model under ±0.5 V voltage supply.

A new simple dual-output second generation current conveyor (DO-CCII) circuit is proposed. Designed in a standard 0.5-μm CMOS process, the circuit operates at ±1.5 V supply voltages with a total power consumption of 106 nW. Main characteristics of the proposed DO-CCII are its simplicity, small silicon area consumption, and not suffering from the body effect of MOS transistors. The proposed circuit is employed to implement a first-order low-pass filter with upper -3 dB cut-off frequency of as low as 3.2 Hz.