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This paper aims to design and simulate a compact dynamic random access memory (DRAM) cell using two-channel spatial wavefunction switched (SWS) field-effect transistor (FET) and two capacitors. One unit of a SWSFET based DRAM cell stores 2-bits, which reduces the overall cell area by 50% as compared to a conventional 1-bit DRAM cell. SWSFETs have two or more vertically stacked quantum well channels as the transport layer between source and drain. In a two quantum channel n-SWSFET, as the gate voltage is raised above threshold, electrons appear in the lower quantum well W2 and this inversion channel connects Source S2 to drain D2. As the gate voltage is further increased, electrons transfer to upper quantum well W1 and now source S1 and drain D1 are connected electrically. Spatial location of electrons allows us to encode as 4 logic states: no electrons 00, electrons in W2 01, electrons is both wells 10 and electrons in well W1. This property of the SWSFET has been shown to implement multi-valued logic circuits. A SWSFET may have 2-4 sources and drains independently operated or connected together depending upon the logic circuit implementation.

Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.

The main memory system has become crucial not only because it has to meet an increasing bandwidth requirement, but also because it has to seamlessly support many concurrently executing applications. In order to improve memory performance, a memory controller with efficient arbitration is necessary. It is well known that memory performance is dependent on the memory access patterns. The offline performance analysis has difficulty analyzing the Dynamic Random Access Memory (DRAM) performance accurately because a huge set of trace patterns is needed. This paper proposes a novel profiler that is synthesized with a memory controller in order to monitor and analyze the memory controller performance at runtime. In this paper, five key metrics for performance evaluation are defined and they are monitored and evaluated at runtime by the proposed profiler. A prototype system with a processor core, a memory controller, DRAM modules, and peripheral devices are implemented on a field-programmable gate array (FPGA) board to carry out the experiments. It has been observed that the worst latency overhead differs for each benchmark. In addition, a new overall overhead estimation method is proposed to estimate the memory access latency overhead in time, and this method can be used to evaluate the performance of a certain memory arbitration method depending on running applications.

We evaluate the initial public offering price of a new DRAM chipmaker in Taiwan in accordance with the compound real call options model of Lin (2002). The worldwide average sales price is the underlying variable, and the average production cost of the new DRAM foundry is the exercise price. The twin security is defined as a portfolio of DRAM manufacturing firms publicly listed in Taiwan stock markets. We estimate the dividend-like yield with two methods, and find that the yield is negative. The negative dividend-like yield results from the negative correlation between the newly constructed DRAM foundry and its twin security, implying the diversification advantage of a new generation of DRAM foundry with a relative low cost of investment opportunity. We solve the critical value for the multivariate normal integral with the secant method, approximating the integral with the lattice method. It has been found that there is only a 4.6% difference between the market IPO price and the estimated one.

Model updating is a widely adopted method to minimize the error between test results from the real structure and outcomes from the finite element (FE) model for obtaining an accurate and reliable FE model of the target structure. However, uncertainties from the environment, excitation and measurement variability can reduce the accuracy of predictions of the updated FE model. The Bayesian model updating method using multiple Markov chains based on differential evolution adaptive metropolis (DREAM) algorithm is explored, which runs multiple chains simultaneously for a global exploration, and it automatically tunes the scale and orientation of the proposal distribution during the evolution of the posterior distribution. The performance of the proposed method is illustrated numerically with a beam model and a three-span rigid frame bridge. Results show that the DREAM algorithm is capable for updating the FE model in civil engineering. It extends the Bayesian model updating method to multiple Markov chains scenario, which provides higher accuracy than single chain algorithm such as the delayed rejection adaptive metropolis-hastings (DRAM) method. Moreover, results from both examples indicate that the proposed method is insensitive to values of initial parameters, which avoid errors resulting from inappropriate prior knowledge of parameters in the FE model updating.

Flash memory has served as an important technology driver due to its many new applications. Despite the fact that NAND flash has out run lithography and other scaling barriers and thus is facing steep challenges, several innovative solutions are being developed to carry its momentum, and it continues to serve as a technology driver in the nanoelectronics era. New devices that are not based on charge storage, on the other hand, are promising to further boost system performance by offering low-power, high-density, and fast latency storage. These new developments should provide the next generation memory and storage solutions that will elevate system performance to a new level.

This paper aims to design and simulate a compact dynamic random access memory (DRAM) cell using two-channel spatial wavefunction switched (SWS) field-effect transistor (FET) and two capacitors. One unit of a SWSFET based DRAM cell stores 2-bits, which reduces the overall cell area by 50% as compared to a conventional 1-bit DRAM cell. SWSFETs have two or more vertically stacked quantum well channels as the transport layer between source and drain. In a two quantum channel n-SWSFET, as the gate voltage is raised above threshold, electrons appear in the lower quantum well W2 and this inversion channel connects Source S2 to drain D2. As the gate voltage is further increased, electrons transfer to upper quantum well W1 and now source S1 and drain D1 are connected electrically. Spatial location of electrons allows us to encode as 4 logic states: no electrons 00, electrons in W2 01, electrons is both wells 10 and electrons in well W1. This property of the SWSFET has been shown to implement multi-valued logic circuits. A SWSFET may have 2-4 sources and drains independently operated or connected together depending upon the logic circuit implementation.

Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.