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A novel ultra-low power two terminal zener voltage reference is designed and implemented. It realizes the concept of using sub-threshold region of the MOSFET to achieve a very low and stable output voltage within a two terminal circuit topology. This proposed voltage reference was fabricated with Global Foundries 0.18-μm CMOS process, consuming only a very small die area of 0.0009 mm². Experimental results, carried out on five different silicon samples, explicitly show that it can yield a stable output voltage of 0.22 V at room temperature. It achieves an average temperature coefficient of 6.4 ppm/°C across a wide temperature range from 0°C to 150°C with a standard deviation of 2 ppm/°C. Furthermore, it achieves an ultra-low power consumption of 2 μW. The load regulation is 20 mV/V. This simple and innovative two terminal device can be used to provide a very low and constant voltage difference between any two nodes in an analog circuit.

A low-power, low-supply, low-complexity all-MOSFET voltage reference is implemented in 0.18$\mu$m CMOS process. With the proposed architecture, the number of the transistors can be reduced to the greatest extent. As a result, the supply voltage can not only be decreased to as low as 0.7V, but the power consumption can also be optimized significantly. Simulation results show that the power consumption is 47nW, at a supply of 0.7V. A temperature coefficient (TC) of 42ppm/${}^{\circ }$C is achieved when the temperature ranges from $-$20${}^{\circ }$C to 80${}^{\circ }$C. At room temperature, the voltage reference features a line regulation (LR) of 2.66%/V.

A novel low line regulation voltage reference (VR) without an amplifier is presented in this paper. The design is achieved by subtracting two voltages which have the same temperature curves. All circuits use only one Bipolar Junction Transistor (BJT) to decrease the area greatly. Designed with the SMIC 0.18$\mu$m CMOS process, the simulation results show that the output voltage is 0.902V at TT process corner when the power supply is larger than 1.7V. The temperature coefficient (TC) is 3.6ppm/${}^{\circ }$C to 7.4ppm/${}^{\circ }$C at different power supplies and process corners. The simulated power supply rejection ratio (PSRR) is $-$80dB at TT process corner when the power supply is 2.5V, and the PSRR at different process corners are almost the same. The line regulation of the proposed circuit is 0.005mV/V.

A 16.4nW, sub-1V voltage reference for ultra-low power low voltage applications is proposed. This design reduces the operating voltage to 0.8V by a BJT voltage divider and decreases the silicon area considerably by eliminating resistors. The PTAT and CTAT are based on SCM structures and a scaled-down $V_{\mathrm{\text{be}}}$, respectively, to improve the process insensitivity. This work is fabricated in 0.18$\mu$m CMOS process with a total area of 0.0033mm². Measured results show that it works properly for supply voltage from 0.8V to 2V. The reference voltage is 467.2mV with standard deviation ($\sigma$) being 12.2 mV and measured TC at best is 38.7ppm/${}^{\circ }$C ranging from $-40^{\circ }$C to 60${}^{\circ }$C. The total power consumption is 16.4nW under the minimum supply voltage at 27${}^{\circ }$C.

A high-precision bandgap voltage reference (BGR) with a novel curvature-compensation scheme is proposed in this paper. The temperature coefficient (TC) can be automatically optimized with a built-in adaptive curvature-compensation technique, which is realized in a digitization control way. An exponential curvature-compensation method is first adopted to reduce the TC in a certain degree, especially in low temperature range. Then, the temperature drift of BGR in higher temperature range can be further minimized by dynamic zero-temperature-coefficient point tracking (ZTCPT) with temperature changes. With the help of proposed adaptive signal processing, the output voltage of BGR can approximately maintain zero TC in a wider temperature range. Verification results of the BGR proposed in this paper, which is implemented in 0.35-$\mu$m BiCMOS process, illustrate that the TC of 1.4ppm/^∘C is realized under the power supply voltage of 3V and the power supply rejection of the proposed circuit is $-65$dB without any filter capacitor.

A regulated power supply with ultra-low-power consumption, high current efficiency, line, load and thermal stability is an essential part of any high precision electronic system with stringent power budget such as biomedical sensors or military surveillance systems. In this paper, we propose an ultra-low-power, MOSFET only, voltage reference to regulator convertor, proficient to work below 1 V with reduced power consumption. The proposed idea incorporates the provision to integrate any voltage reference module to a comparator-based circuit so as to transform it to a voltage regulator having similar temperature coefficient (TC) and line regulation as that of the interfaced voltage reference. It is also able to produce a reliable output accounting to load fluctuations. The circuit is simulated in 0.18$\mu$m CMOS technology using Cadence Virtuoso simulation suit. The complete circuit was found to draw a quiescent current of 319.9 pA with a notable current efficiency of 99.99997% at 27^∘C on driving a load of 1mA along with a Power Supply Rejection Ratio (PSRR) of $-117$dB additional to that of the reference. The proposed circuit will occupy an area of 0.00064mm² and offer a TC as low as 1.7077 ppm/^∘C. The whole MOS approach facilitates a reduction in die area and process simplicity.

The paper presents a low supply voltage CMOS voltage reference with low line sensitivity and high PSRR. Generally, the reference voltage is obtained using both complementary-to-absolute-temperature (CTAT) current and proportional-to-absolute-temperature (PTAT) current. This technique increases the complexity and area of the reference circuit. To overcome these drawbacks, the temperature compensated reference voltage has been proposed using only CTAT currents. Mostly, the CTAT current generators are simple, power-efficient, and area-efficient as compared to the PTAT current generators. The negative feedback loop has been formed in the proposed design to obtain a supply independent CTAT current and to avoid the use of startup drivers. The proposed circuit has been designed using Cadence virtuoso analog design environment in BSIM3V3 180nm CMOS technology. The simulation results of the proposed circuit show a reference voltage of 312mV with a temperature coefficient (TC) of 38.85ppm/^∘C over a wide temperature range of $-40^{\circ }$C to 125^∘C with a supply voltage of 0.8V. The line sensitivity is 0.027% $∕\mathrm{\text{V}}$ with a supply voltage ranging from 0.8V to 3V. The power supply rejection ratio (PSRR) without using any capacitive filter is observed as $-80.84$ and $-71.66$dB at 100Hz and 100kHz frequency, respectively. The circuit is simple and occupies a chip area of 0.0027mm².

In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-$\mu$m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494mV with temperature coefficient (TC) of 58.4ppm/^∘C across $-40^{\circ }$C to 85^∘C; while the consuming power is lowered to 3.48nW at the minimum supply of 0.8V. The line sensitivity is 0.7%/V for the supply voltages from 0.8V to 1.8V, whereas the power supply ripple rejection (PSRR) is $-$49.06dB at 1Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2mV with $\sigma$/$\mu$ of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.

This paper presents a novel sub-1-V CMOS voltage reference with high power supply rejection ratio (PSRR), low line sensitivity, and low supply voltage. CMOS voltage references available in the literature use a self-biased cascode branch consisting of two MOS transistors operating in the subthreshold region to generate the proportional-to-absolute-temperature (PTAT) voltage only, whereas extra circuitry is required to generate the complementary-to-absolute-temperature (CTAT) voltage for temperature compensation. But in the proposed sub-1-V CMOS voltage reference, both the PTAT and CTAT voltages are generated using a single self-biased cascode branch. Two operational amplifiers in negative feedback topology are used to convert the PTAT and CTAT voltages into PTAT and CTAT currents, respectively, which help to enhance the stability and PSRR of the proposed voltage reference. The proposed voltage reference has been designed and simulated in 180-nm standard CMOS technology using Cadence Virtuoso Analog Design Environment. The proposed voltage reference achieves an output reference voltage of 424.85mV with a temperature coefficient of 29.5ppm/^∘C for the temperatures ranging from $-55^{\circ }$C to 125^∘C at a supply voltage of 0.8V. A line sensitivity of 0.0035%/V is achieved for the supply voltage varying from 0.8V to 5V at nominal temperature (27^∘C). A PSRR of $-$91.69dB is observed for the frequencies ranging from 1Hz to 10kHz at nominal conditions without using any capacitive filter. Also, the output noises of the proposed design at nominal conditions for the frequencies of 1Hz and 10kHz are obtained as 2.37$\mu$V/$\surd$Hz and 45.26nV/$\surd$Hz, respectively.

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment.

In this paper we demonstrate that by exploiting the non linear characteristic of low noise PN junction diodes, a very low noise, high stability voltage reference can be obtained starting from a conventional solid state series voltage reference. In order to obtain such a result, a series connection of N identical diodes is supplied in the forward region of the I-V characteristic by means of a proper resistance. While the DC voltage drop across the diodes can be a large fraction of the voltage supplied by the reference, the noise introduced by the reference itself is reduced by a much larger factor because of the low value of the small signal equivalent resistance of the diodes. In its simplest implementation, such a voltage source would suffer from a relatively high temperature dependence of the supplied voltages because of the intrinsic properties of PN junctions. However, by resorting to a proper temperature control circuit, high stability can be obtained. As an example, by employing an AD586 voltage reference and with N = 4, a 2.560 V reference has been obtained with a stability over temperature better that 50 μV/°C and a voltage noise as low as 2 × 10⁻¹⁵, 6 × 10⁻¹⁷ and 1.5 × 10⁻¹⁷V²/Hz at 100 mHz, 1 Hz and for frequencies larger than 10 Hz, respectively.