3.48-nW 58.4ppm/°C Sub-threshold CMOS Voltage Reference with Four Transistors and Two Resistors
Abstract
In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-μm CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494mV with temperature coefficient (TC) of 58.4ppm/∘C across −40∘C to 85∘C; while the consuming power is lowered to 3.48nW at the minimum supply of 0.8V. The line sensitivity is 0.7%/V for the supply voltages from 0.8V to 1.8V, whereas the power supply ripple rejection (PSRR) is −49.06dB at 1Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2mV with σ/μ of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.
This paper was recommended by Regional Editor Giuseppe Ferri.
