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Wake-up receivers (WuRxs) allow wireless sensor nodes to run on battery power while maintaining asynchronous, low-latency communication. This paper focuses on WuRxs based on low-frequency pattern matchers (LFPMs). Many recent studies either investigate physical WuRx implementations or simulate WuRx-based protocols. Our goal is to address the challenges that arise when realizing WuRx-based protocols in hardware. These challenges are, that a packet activates unwanted WuRxs, an unreliable address space, and missing cluster broadcast capabilities. The proposed separation sequences and run-length limited patterns ensure a reliable address space. WuRxs based on LFPMs use a fixed pattern matching. Cluster broadcasts are enabled by the proposed variable Manchester coding. Typically, LFPMs use Manchester coding with an efficiency of only 0.5 bit/symbol. We introduce two non-Manchester coding techniques with higher efficiency: lookup table-based coding with an efficiency of 0.71 and 3S2B coding with an efficiency of 0.67.

As the Bluetooth devices for the internet of things require extremely low-power dissipation to maintain longer battery life, a low-noise amplifier (LNA) as the main power-consuming part in the circuit needs more current-efficient topologies on power saving. This paper proposes a low-noise transconductance amplifier that combines the techniques of passive impendence transformation, $g_m$-boosting technique, and current reuse, leading to a low power under the 1.2 V power supply. The transformer-based $g_m$-boosted structure is applied in the four-transistor-stacked current-reuse topology leading to a $12\times$ power saving. The proposed LNA simulated in 65 nm CMOS shows the NF of 3.3 dB and the IIP3 of −8 dBm, respectively, while dissipating 87 $\mu$W dc power. Compared to the previous low-power LNA, this design has fairly low-power consumption and low NF while other performance metrics remain competitive.

A novel ultra-low power two terminal zener voltage reference is designed and implemented. It realizes the concept of using sub-threshold region of the MOSFET to achieve a very low and stable output voltage within a two terminal circuit topology. This proposed voltage reference was fabricated with Global Foundries 0.18-μm CMOS process, consuming only a very small die area of 0.0009 mm². Experimental results, carried out on five different silicon samples, explicitly show that it can yield a stable output voltage of 0.22 V at room temperature. It achieves an average temperature coefficient of 6.4 ppm/°C across a wide temperature range from 0°C to 150°C with a standard deviation of 2 ppm/°C. Furthermore, it achieves an ultra-low power consumption of 2 μW. The load regulation is 20 mV/V. This simple and innovative two terminal device can be used to provide a very low and constant voltage difference between any two nodes in an analog circuit.

In this paper, a wide input range supply voltage tolerant capacitive sensor readout circuit using on-chip solar cell is presented. Based on capacitance controlled oscillators (CCOs) for ultra-low voltage/power consumption, the sensor readout circuit is directly powered by the on-chip solar cell to improve the overall system energy efficiency. An extended sensing range with high sensing accuracy is achieved using a two-step successive approximation register (SAR) and delta-sigma ($\Delta \Sigma$) analog-to-digital (A/D) conversion (ADC) scheme. Digital controls are generated on-chip using a customized sub-threshold digital standard cell library. Systematic error analysis and optimization including the finite switch on-resistance, buffer input-dependent delay, and SAR quantization nonlinearity are also outlined. High power supply rejection ratio (PSRR) is ensured by using a pseudo-differential topology with ratiometric readout. The complete sensing system is implemented using a standard 0.18$\mu$m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the readout circuit achieves a wide input range from 1.5pF to 6.5pF with a worst case PSRR of 0.5% from 0.3V to 0.42V (0.67% from 0.3V to 0.6V). With a 3.5pF input capacitance and a 0.3V supply, the $\Delta \Sigma$ stage achieves a resolution of 7.1-bit (corresponding to a capacitance of 2.2fF/LSB) with a conversion frequency of 371Hz. With an average power consumption of 40nW and a sampling frequency of 47.5kHz, a figure-of-merit (FoM) of 0.78pJ/conv-step is achieved.

This paper reports an ultra-low power received signal strength indicator (RSSI) for low frequency (LF) wake-up receiver. Topology theory analysis and subthreshold operation are performed to lower power consumption. Each gain stage of the subthreshold limiting amplifier (LA) employs cascade diode-connected loads to obtain high output impedance while maintaining low power. An offset cancelation circuit with different tail currents, which also operates in the subthreshold region, is employed to reduce the DC offset voltage. Unbalanced source-coupled pairs of subthreshold devices adopted in the full-wave rectification are optimized. A 45dB input dynamic range and $a\pm 1$dB indicating error are achieved at 125KHz frequency. The prototype occupies an active area of 0.39$\times$0.28mm using CSMC 0.153-$\mu$m complementary metal-oxide-semiconductor (CMOS) technology. With a 1.8V supply voltage, the overall current consumption is only 6$\mu$A.

A 16.4nW, sub-1V voltage reference for ultra-low power low voltage applications is proposed. This design reduces the operating voltage to 0.8V by a BJT voltage divider and decreases the silicon area considerably by eliminating resistors. The PTAT and CTAT are based on SCM structures and a scaled-down $V_{\mathrm{\text{be}}}$, respectively, to improve the process insensitivity. This work is fabricated in 0.18$\mu$m CMOS process with a total area of 0.0033mm². Measured results show that it works properly for supply voltage from 0.8V to 2V. The reference voltage is 467.2mV with standard deviation ($\sigma$) being 12.2 mV and measured TC at best is 38.7ppm/${}^{\circ }$C ranging from $-40^{\circ }$C to 60${}^{\circ }$C. The total power consumption is 16.4nW under the minimum supply voltage at 27${}^{\circ }$C.

A 36-kHz frequency locked on-chip oscillator is proposed, the proportional-to-absolute temperature (PTAT) current and voltage generator is presented to eliminate conventional temperature-compensated resistors. The resistorless approach reduces the process variation of frequency and the chip area. The oscillator is fabricated in 0.18-$\mu$m standard CMOS process with an active area of 0.072mm². The temperature coefficient of frequency is 48ppm/^∘C at best and 82.5ppm/^∘C on average over $-40^{}$–70^∘C and the frequency spread is 1.43% ($\sigma$/$\mu )$ without calibration. The supply voltage sensitivity is 1.8%/V in the range from 0.65V to 1V and the power consumption is 95nW under the supply voltage of 0.65V.

This paper explores the design and analysis of 20nm tunnel transistor-based Exclusive-OR (Ex-OR) gates and half-adder cells with circuit interaction (co-design) approach for energy efficient and reliable computing architectures at scaled supply voltages (50–300mV). TFETs have attracted much attention recently for energy efficient system designs. The circuit interaction is made possible for designing more consistent functional architectures at the minimum power supply of 50–300mV. Using this technique, the core computational blocks of basic adder blocks and Ex-OR gates are designed with TFET as a fundamental device and the whole design procedure is elaborated in this paper. The primary classifications of Tunnel FETs, viz. Homo-junction TFET (HoJn TFET) and Hetero-junction TFETs (HeJn TFET) are investigated thoroughly under different constraints specifically at the device configurations. By considering the above-mentioned subtypes of TFETs, three variants of Ex-OR primitive gates are modeled and are named with respect to the use of transistors as static complementary TFET-12T (SC12T), Transmission Gate logic-8T (TG8T) and Improved Transmission Gate logic-6T (ITG6T) Ex-OR gate designs. The benchmarking of the proposed gates is done using double-gate Si FinFET at 20nm technology. Amongst all the three proposed Ex-OR designs of SC12T, TG8T and ITG6T in addition to that of LVT and HVT FinFET/CMOS, only ITG6T is the designer’s choice by offering the minimum power consumption as well as high energy, improved choice compared to the other two styles of designs and also when robustness and reliability are taken into account, SC12T and TG8T designs are not providing the full swing of outputs. The minute glitch with that of ITG6T designs is a lesser reliability feature and for this the best alternative is TFET TG8T by providing suppressed over shoots and enhanced transition speed. From the performed multi simulations under different critical conditions and at supply voltage of 100mV, it is being demonstrated that the energy efficient circuit option is the SC12T and ITG6T Ex-OR designs which are validated with the steep slope characteristics of TFET’s and also these two designs offer reliability advantage. The major restrictions from the energy efficiency issues are eliminated and disclosed in the HoJn TFETs and HeJn TFET by using circuit co-design methodology and TFETs steep slope characteristics.

In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-$\mu$m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494mV with temperature coefficient (TC) of 58.4ppm/^∘C across $-40^{\circ }$C to 85^∘C; while the consuming power is lowered to 3.48nW at the minimum supply of 0.8V. The line sensitivity is 0.7%/V for the supply voltages from 0.8V to 1.8V, whereas the power supply ripple rejection (PSRR) is $-$49.06dB at 1Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2mV with $\sigma$/$\mu$ of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.